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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-12 22:50:55 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-12 22:50:55 +0100 |
| commit | be5048f16653787106945122ba043b3a8b42f30c (patch) | |
| tree | b609ccc12b1b4cf93da7b717c25c83418ef46d82 /drivers/tsec.h | |
| parent | ca27381df15c99c7b542f847359a8a4543f24d2a (diff) | |
| download | u-boot-imx-be5048f16653787106945122ba043b3a8b42f30c.zip u-boot-imx-be5048f16653787106945122ba043b3a8b42f30c.tar.gz u-boot-imx-be5048f16653787106945122ba043b3a8b42f30c.tar.bz2 | |
Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver
Patch by Murray Jensen, 08 Jul 2005
Diffstat (limited to 'drivers/tsec.h')
| -rw-r--r-- | drivers/tsec.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/tsec.h b/drivers/tsec.h index e92b53a..b55b299 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -168,6 +168,16 @@ #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ +/* DP83865 Control register values */ +#define MIIM_DP83865_CR_INIT 0x9200 + +/* DP83865 Link and Auto-Neg Status Register */ +#define MIIM_DP83865_LANR 0x11 +#define MIIM_DP83865_SPD_MASK 0x0018 +#define MIIM_DP83865_SPD_1000 0x0010 +#define MIIM_DP83865_SPD_100 0x0008 +#define MIIM_DP83865_DPX_FULL 0x0002 + #define MIIM_READ_COMMAND 0x00000001 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN |