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authorpekon gupta <pekon@ti.com>2014-07-18 17:59:40 +0530
committerTom Rini <trini@ti.com>2014-07-25 16:26:12 -0400
commit77cd89e75563742aa32cf3d216ac9ff649d1d70e (patch)
tree3d406770cd972f2ef88bec049ed48025cde1e831 /drivers/tpm
parent8c16dd6fa7de448b36778275b456bf4ea53c3306 (diff)
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ARM: omap: fix GPMC address-map size for NAND and NOR devices
Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform 1) NAND device are not directly memory-mapped to CPU address-space, they are indirectly accessed via following GPMC registers: - GPMC_NAND_COMMAND_x - GPMC_NAND_ADDRESS_x - GPMC_NAND_DATA_x Therefore from CPU's point of view, NAND address-map can be limited to just above register addresses. But GPMC chip-select address-map can be configured in granularity of 16MB only. So this patch uses GPMC_SIZE_16M for all NAND devices. 2) NOR device are directly memory-mapped to CPU address-space, so its address-map size depends on actual addressable region in NOR FLASH device. So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map size configuration. Signed-off-by: Pekon Gupta <pekon@ti.com>
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