Merge branch 'master' of git://git.denx.de/u-boot-arm

Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>

1 files changed, 19 insertions, 20 deletions

diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index bb865b7..ffa3c1d 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -40,17 +40,6 @@
 
 #define MXSSSP_SMALL_TRANSFER	512
 
-/*
- * CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI
- *                            host. Use with utmost caution!
- *
- *                            Enabling this is not yet recommended since this
- *                            still doesn't support transfers to/from unaligned
- *                            addresses. Therefore this driver will not work
- *                            for example with saving environment. This is
- *                            caused by DMA alignment constraints on MXS.
- */
-
 struct mxs_spi_slave {
 	struct spi_slave	slave;
 	uint32_t		max_khz;
@@ -70,7 +59,7 @@ void spi_init(void)
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
 	/* MXS SPI: 4 ports and 3 chip selects maximum */
-	if (bus > 3 || cs > 2)
+	if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
 		return 0;
 	else
 		return 1;
@@ -92,7 +81,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (!mxs_slave)
 		return NULL;
 
-	if (mxs_dma_init_channel(bus))
+	if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
 		goto err_init;
 
 	mxs_slave->slave.bus = bus;
@@ -168,7 +157,12 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
 
 	while (length--) {
 		/* We transfer 1 byte */
+#if defined(CONFIG_MX23)
+		writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
+		writel(1, &ssp_regs->hw_ssp_ctrl0_set);
+#elif defined(CONFIG_MX28)
 		writel(1, &ssp_regs->hw_ssp_xfer_size);
+#endif
 
 		if ((flags & SPI_XFER_END) && !length)
 			mxs_spi_end_xfer(ssp_regs);
@@ -226,6 +220,12 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 	int tl;
 	int ret = 0;
 
+#if defined(CONFIG_MX23)
+	const int mxs_spi_pio_words = 1;
+#elif defined(CONFIG_MX28)
+	const int mxs_spi_pio_words = 4;
+#endif
+
 	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
 
 	memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
@@ -281,7 +281,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 
 		dp->cmd.data |=
 			((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
-			(4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+			(mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
 			MXS_DMA_DESC_HALT_ON_TERMINATE |
 			MXS_DMA_DESC_TERMINATE_FLUSH;
 
@@ -298,15 +298,19 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 		}
 
 		/*
-		 * Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is
+		 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
+		 * case of MX28, write only CTRL0 in case of MX23 due
+		 * to the difference in register layout. It is utterly
 		 * essential that the XFER_SIZE register is written on
 		 * a per-descriptor basis with the same size as is the
 		 * descriptor!
 		 */
 		dp->cmd.pio_words[0] = ctrl0;
+#ifdef CONFIG_MX28
 		dp->cmd.pio_words[1] = 0;
 		dp->cmd.pio_words[2] = 0;
 		dp->cmd.pio_words[3] = tl;
+#endif
 
 		mxs_dma_desc_append(dmach, dp);
 
@@ -332,12 +336,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	char dummy;
 	int write = 0;
 	char *data = NULL;
-
-#ifdef CONFIG_MXS_SPI_DMA_ENABLE
 	int dma = 1;
-#else
-	int dma = 0;
-#endif
 
 	if (bitlen == 0) {
 		if (flags & SPI_XFER_END) {