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| author | Simon Glass <sjg@chromium.org> | 2011-11-05 04:46:50 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-12-24 10:23:31 +0100 |
| commit | 4560c7decc1b13121072621cee9874e042c059b7 (patch) | |
| tree | 4103f6a49fe73a8d1ff4754e78d2079094f901e4 /drivers/spi | |
| parent | cb93481268904df3447fbe8b0ccb2862967efc26 (diff) | |
| download | u-boot-imx-4560c7decc1b13121072621cee9874e042c059b7.zip u-boot-imx-4560c7decc1b13121072621cee9874e042c059b7.tar.gz u-boot-imx-4560c7decc1b13121072621cee9874e042c059b7.tar.bz2 | |
tegra2: spi: Support SPI / UART switch
Add the SPI / UART switch logic into the Tegra2 SPI driver so that it
can co-exist with the NS16550 UART.
We need the ns16550.h header for NS16550_t for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/tegra2_spi.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c index fdcad09..56cb229 100644 --- a/drivers/spi/tegra2_spi.c +++ b/drivers/spi/tegra2_spi.c @@ -28,9 +28,11 @@ #include <spi.h> #include <asm/io.h> #include <asm/gpio.h> +#include <ns16550.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> #include <asm/arch/pinmux.h> +#include <asm/arch/uart-spi-switch.h> #include <asm/arch/tegra2_spi.h> struct tegra_spi_slave { @@ -128,6 +130,16 @@ int spi_claim_bus(struct spi_slave *slave) */ pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); pinmux_tristate_disable(PINGRP_LSPI); + +#ifndef CONFIG_SPI_UART_SWITCH + /* + * NOTE: + * Only set PinMux bits 3:2 to SPI here on boards that don't have the + * SPI UART switch or subsequent UART data won't go out! See + * spi_uart_switch(). + */ + /* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */ +#endif return 0; } @@ -145,6 +157,8 @@ void spi_cs_activate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); + pinmux_select_spi(); + /* CS is negated on Tegra, so drive a 1 to get a 0 */ setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); } |