diff options
author | Wolfgang Denk <wd@denx.de> | 2011-10-28 00:15:19 +0200 |
---|---|---|
committer | Wolfgang Denk <wd@denx.de> | 2011-10-28 00:15:19 +0200 |
commit | 87a5d601031652293ec4b729fdb7ee01bbd940a8 (patch) | |
tree | 91ede3ee45b228736c1876a700024782d7bc2032 /drivers/spi/armada100_spi.c | |
parent | 606a76f8ef479e42ae4d06f8f3ce87e9a1c72acf (diff) | |
parent | 37fc0ed268dc5acacd3a83adafa26eb1a84e90af (diff) | |
download | u-boot-imx-87a5d601031652293ec4b729fdb7ee01bbd940a8.zip u-boot-imx-87a5d601031652293ec4b729fdb7ee01bbd940a8.tar.gz u-boot-imx-87a5d601031652293ec4b729fdb7ee01bbd940a8.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
ARM: Add Calxeda Highbank platform
dkb: make mmc command as default enabled
Marvell: dkb: add mmc support
ARM: pantheon: add mmc definition
davinci: remove config.mk file from the sources
ARM:AM33XX: Add support for TI AM335X EVM
ARM:AM33XX: Added timer support
ARM:AM33XX: Add emif/ddr support
ARM:AM33XX: Add clock definitions
ARM:AM33XX: Added support for AM33xx
omap3/emif4: fix registers definition
davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
davinci: emac: add support for more than 1 PHYs
davinci: emac: add new features to autonegotiate for EMAC
da850evm: Move LPSC configuration to board_early_init_f()
omap4_panda: Build in cmd_gpio support on panda
omap: Don't use gpio_free to change direction to input
mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
OMAP3: overo : Add environment variable optargs to bootargs
OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
OMAP3: overo : Use ttyO2 instead of ttyS2.
da830: add support for NAND boot mode
dm36x: revert cache disable patch
dm644X: revert cache disable patch
devkit8000: Add malloc space
omap: spl: fix build break due to changes in FAT
OMAP3 SPL: Provide weak omap_rev_string
omap: beagle: Use ubifs instead of jffs2 for nand boot
omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
omap: overo: Configure mux for gpio10
SPL: Add DMA library
omap3: Add interface for omap3 DMA
omap3: Add DMA register accessors
omap3: Add Base register for DMA
arm, davinci: add missing LSPC define for MMC/SD1
U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
DaVinci: correct MDSTAT.STATE mask
omap4: splitting padconfs into common, 4430 and 4460
omap4: adding revision detection for 4460 ES1.1
omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
gplug: fixed build error as a result of code cleanup patch
kirkwood_spi: add dummy spi_init()
gpio: mvmfp: reduce include platform file
ARM: orion5x: reduce dependence of including platform file
serial: reduce include platform file for marvell chip
ARM: kirkwood: reduce dependence of including platform file
ARM: armada100: reduce dependence of including platform file
ARM: pantheon: reduce dependence of including platform file
Armada100: Add env storage support for Marvell gplugD
Armada100: Add SPI flash support for Marvell gplugD
Armada100: Add SPI support for Marvell gplugD
SPI: Add SPI driver support for Marvell Armada100
dreamplug: initial board support.
imx: fix coding style
misc: pmic: drop old Freescale's pmic driver
MX31: mx31pdk: use new pmic driver
MX31: mx31ads: use new pmic driver
MX31: mx31_litekit: use new pmic driver
MX5: mx53evk: use new pmic driver
MX5: mx51evk: use new pmic driver
MX35: mx35pdk: use new pmic driver
misc: pmic: addI2C support to pmic_fsl driver
misc: pmic: use I2C_SET_BUS in pmic I2C
MX5: efikamx/efikasb: use new pmic driver
MX3: qong: use new pmic driver
RTC: Switch mc13783 to generic pmic code
MX5: vision2: use new pmic driver
misc: pmic: Freescale PMIC switches to generic PMIC driver
misc:pmic:samsung Enable PMIC driver at GONI target
misc:pmic:max8998 MAX8998 support at a new PMIC driver.
misc:pmic:core New generic PMIC driver
mx31pdk: Remove unneeded config
mx31: provide readable WEIM CS accessor
MX51: vision2: Set global macros
I2C: Add i2c_get/set_speed() to mxc_i2c.c
ARM: Update mach-types
devkit8000: Add config to enable SPL MMC boot
devkit8000: protect board_mmc_init
arm, post: add missing post_time_ms for arm
cosmetic, post: Codingstyle cleanup
arm, logbuffer: make it compileclean
tegra2: Enable MMC for Seaboard
tegra2: Add more pinmux functions
tegra2: Rename PIN_ to PINGRP_
tegra2: Add more clock functions
tegra2: Clean up board code a little
tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
Diffstat (limited to 'drivers/spi/armada100_spi.c')
-rw-r--r-- | drivers/spi/armada100_spi.c | 228 |
1 files changed, 228 insertions, 0 deletions
diff --git a/drivers/spi/armada100_spi.c b/drivers/spi/armada100_spi.c new file mode 100644 index 0000000..7384c9c --- /dev/null +++ b/drivers/spi/armada100_spi.c @@ -0,0 +1,228 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> + * + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Based on SSP driver + * Written-by: Lei Wen <leiwen@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include <common.h> +#include <malloc.h> +#include <spi.h> + +#include <asm/io.h> +#include <asm/arch/spi.h> +#include <asm/gpio.h> + +#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave) + +struct armd_spi_slave { + struct spi_slave slave; + struct ssp_reg *spi_reg; + u32 cr0, cr1; + u32 int_cr1; + u32 clear_sr; + const void *tx; + void *rx; + int gpio_cs_inverted; +}; + +static int spi_armd_write(struct armd_spi_slave *pss) +{ + int wait_timeout = SSP_FLUSH_NUM; + while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF)) + ; + if (!wait_timeout) { + debug("%s: timeout error\n", __func__); + return -1; + } + + if (pss->tx != NULL) { + writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr); + ++pss->tx; + } else { + writel(0, &pss->spi_reg->ssdr); + } + return 0; +} + +static int spi_armd_read(struct armd_spi_slave *pss) +{ + int wait_timeout = SSP_FLUSH_NUM; + while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE)) + ; + if (!wait_timeout) { + debug("%s: timeout error\n", __func__); + return -1; + } + + if (pss->rx != NULL) { + *(u8 *)pss->rx = readl(&pss->spi_reg->ssdr); + ++pss->rx; + } else { + readl(&pss->spi_reg->ssdr); + } + return 0; +} + +static int spi_armd_flush(struct armd_spi_slave *pss) +{ + unsigned long limit = SSP_FLUSH_NUM; + + do { + while (readl(&pss->spi_reg->sssr) & SSSR_RNE) + readl(&pss->spi_reg->ssdr); + } while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--); + + writel(SSSR_ROR, &pss->spi_reg->sssr); + + return limit; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct armd_spi_slave *pss = to_armd_spi_slave(slave); + + gpio_set_value(slave->cs, pss->gpio_cs_inverted); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct armd_spi_slave *pss = to_armd_spi_slave(slave); + + gpio_set_value(slave->cs, !pss->gpio_cs_inverted); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct armd_spi_slave *pss; + + pss = malloc(sizeof(*pss)); + if (!pss) + return NULL; + + pss->slave.bus = bus; + pss->slave.cs = cs; + pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT); + + pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE; + + pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) | + (SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT); + pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); + pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) + | (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); + + pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; + pss->clear_sr = SSSR_ROR | SSSR_TINT; + + pss->gpio_cs_inverted = mode & SPI_CS_HIGH; + gpio_set_value(cs, !pss->gpio_cs_inverted); + + return &pss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct armd_spi_slave *pss = to_armd_spi_slave(slave); + + free(pss); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct armd_spi_slave *pss = to_armd_spi_slave(slave); + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + if (spi_armd_flush(pss) == 0) + return -1; + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct armd_spi_slave *pss = to_armd_spi_slave(slave); + uint bytes = bitlen / 8; + unsigned long limit; + int ret = 0; + + if (bitlen == 0) + goto done; + + /* we can only do 8 bit transfers */ + if (bitlen % 8) { + flags |= SPI_XFER_END; + goto done; + } + + if (dout) + pss->tx = dout; + else + pss->tx = NULL; + + if (din) + pss->rx = din; + else + pss->rx = NULL; + + if (flags & SPI_XFER_BEGIN) { + spi_cs_activate(slave); + writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1); + writel(TIMEOUT_DEF, &pss->spi_reg->ssto); + writel(pss->cr0, &pss->spi_reg->sscr0); + } + + while (bytes--) { + limit = SSP_FLUSH_NUM; + ret = spi_armd_write(pss); + if (ret) + break; + + while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--) + udelay(1); + + ret = spi_armd_read(pss); + if (ret) + break; + } + + done: + if (flags & SPI_XFER_END) { + /* Stop SSP */ + writel(pss->clear_sr, &pss->spi_reg->sssr); + clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1); + writel(0, &pss->spi_reg->ssto); + spi_cs_deactivate(slave); + } + + return ret; +} |