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| author | Wolfgang Denk <wd@denx.de> | 2008-04-08 00:04:39 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-04-08 00:04:39 +0200 |
| commit | 5c395393cc9b85b14c5481dbcab6b67b54f31622 (patch) | |
| tree | 888e8cd55173a99f636b19e2813e3dfe6afe3d44 /drivers/serial | |
| parent | e59af4b611408adcdfb5e19bc5194a7d1f8b4dc3 (diff) | |
| parent | 280df59a8d62c6e74c281b1cb7e2052df4d6cb00 (diff) | |
| download | u-boot-imx-5c395393cc9b85b14c5481dbcab6b67b54f31622.zip u-boot-imx-5c395393cc9b85b14c5481dbcab6b67b54f31622.tar.gz u-boot-imx-5c395393cc9b85b14c5481dbcab6b67b54f31622.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-sh
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/serial_sh.c | 70 |
1 files changed, 38 insertions, 32 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 70fd23f..522f96d 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -37,39 +37,46 @@ #define SCFCR (vu_short *)(SCIF_BASE + 0x18) #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ -#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ -#define SCFTDR (vu_char *)(SCIF_BASE + 0x20) -#define SCFRDR (vu_char *)(SCIF_BASE + 0x24) +# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ +# define SCFTDR (vu_char *)(SCIF_BASE + 0x20) +# define SCFRDR (vu_char *)(SCIF_BASE + 0x24) #else -#define SCFTDR (vu_char *)(SCIF_BASE + 0xC) -#define SCFSR (vu_short *)(SCIF_BASE + 0x10) -#define SCFRDR (vu_char *)(SCIF_BASE + 0x14) +# define SCFTDR (vu_char *)(SCIF_BASE + 0xC) +# define SCFSR (vu_short *)(SCIF_BASE + 0x10) +# define SCFRDR (vu_char *)(SCIF_BASE + 0x14) #endif -#if defined(CONFIG_SH4A) -#define SCRFDR (vu_short *)(SCIF_BASE + 0x20) -#define SCSPTR (vu_short *)(SCIF_BASE + 0x24) -#define SCLSR (vu_short *)(SCIF_BASE + 0x28) -#define SCRER (vu_short *)(SCIF_BASE + 0x2C) -#define LSR_ORER 1 -#elif defined (CONFIG_SH4) -#define SCSPTR (vu_short *)(SCIF_BASE + 0x20) -#define SCLSR (vu_short *)(SCIF_BASE + 0x24) -#define LSR_ORER 1 -#elif defined (CONFIG_SH3) -#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ -#define SCLSR (vu_short *)(SCIF_BASE + 0x24) -#define LSR_ORER 0x0200 -#else -#define SCLSR SCFSR /* SCSSR */ -#define LSR_ORER 1 -#endif +#if defined(CONFIG_CPU_SH7780) || \ + defined(CONFIG_CPU_SH7785) +# define SCRFDR (vu_short *)(SCIF_BASE + 0x20) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x28) +# define SCRER (vu_short *)(SCIF_BASE + 0x2C) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0xFF +#elif defined(CONFIG_CPU_SH7750) || \ + defined(CONFIG_CPU_SH7751) || \ + defined(CONFIG_CPU_SH7722) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x20) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F +#elif defined(CONFIG_CPU_SH7720) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 0x0200 +# define FIFOLEVEL_MASK 0x1F +#elif defined(CONFIG_CPU_SH7710) + defined(CONFIG_CPU_SH7712) +# define SCLSR SCFSR /* SCSSR */ +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F #endif +/* SCBRR register value setting */ #if defined(CONFIG_CPU_SH7720) -#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #else /* Generic SuperH */ -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif #define SCR_RE (1 << 4) @@ -105,14 +112,13 @@ int serial_init (void) return 0; } -static int serial_tx_fifo_level (void) -{ - return (*SCFDR >> 8) & 0x1F; -} - static int serial_rx_fifo_level (void) { - return (*SCFDR >> 0) & 0x1F; +#if defined(CONFIG_SH4A) + return (*SCRFDR >> 0) & FIFOLEVEL_MASK; +#else + return (*SCFDR >> 0) & FIFOLEVEL_MASK; +#endif } void serial_raw_putc (const char c) |