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| author | Tom Rini <trini@konsulko.com> | 2016-01-03 10:32:24 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-01-03 10:32:24 -0500 |
| commit | f1993ca066100fcaba7d49fecae0ef604e5807e2 (patch) | |
| tree | 5439c5cdd14b34ff2085b4876472a44349c15843 /drivers/serial | |
| parent | d83c25c318564080ce647795e5ee49133b97e87d (diff) | |
| parent | ccf4326bac0371774265be0a8b13c150b445e703 (diff) | |
| download | u-boot-imx-f1993ca066100fcaba7d49fecae0ef604e5807e2.zip u-boot-imx-f1993ca066100fcaba7d49fecae0ef604e5807e2.tar.gz u-boot-imx-f1993ca066100fcaba7d49fecae0ef604e5807e2.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/serial_mxc.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index d6cf1d8..51485c0 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -75,6 +75,7 @@ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ #define USR1_RTSS (1<<14) /* RTS pin status */ @@ -135,6 +136,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define TXTL 2 /* reset default */ +#define RXTL 1 /* reset default */ +#define RFDIV 4 /* divide input clock by 2 */ + static void mxc_serial_setbrg(void) { u32 clk = imx_get_uartclk(); @@ -142,7 +147,9 @@ static void mxc_serial_setbrg(void) if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; - __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF) + | (TXTL << UFCR_TXTL_SHF) + | (RXTL << UFCR_RXTL_SHF); __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); |