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authorMichal Simek <michal.simek@xilinx.com>2016-02-03 15:16:51 +0100
committerMichal Simek <michal.simek@xilinx.com>2016-02-22 16:21:04 +0100
commit6cd0f2a6cd40bdf3d06d60dab86f425285475ea0 (patch)
tree7de0768917733b88f256a22856b5bdd927372ec6 /drivers/serial
parentd82d63cc9bc57952cefdd539f7d5c6e9da608cec (diff)
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serial: zynq: Change logic in putc
Sync logic with Linux kernel where TX empty flag is checked before char is sent. This logic is fixing problem with console on zynqmp platform. For example: DRAM: 2 GiB Enabling Caches... EL Level: �� sdhci@ff170000: 0 Using default environment Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/serial_zynq.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index e79d997..66d54e3 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -19,7 +19,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */
#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
@@ -97,7 +97,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs)
static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
{
- if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
+ if (!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
return -EAGAIN;
writel(c, &regs->tx_rx_fifo);