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| author | Phil Edworthy <PHIL.EDWORTHY@renesas.com> | 2012-05-15 22:15:51 +0000 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2012-05-28 09:12:54 +0900 |
| commit | 99744b7e342014082609572af01bb6964e0f5a5a (patch) | |
| tree | 0f3f78df5bf7d823fc5ef7e840edea5d81e08272 /drivers/serial | |
| parent | a80a661989d35620465da85d9d9f8179e9c9e843 (diff) | |
| download | u-boot-imx-99744b7e342014082609572af01bb6964e0f5a5a.zip u-boot-imx-99744b7e342014082609572af01bb6964e0f5a5a.tar.gz u-boot-imx-99744b7e342014082609572af01bb6964e0f5a5a.tar.bz2 | |
sh: Add SH7269 device and RSK2+SH7269 board
This is an sh2a device (max 266MHz) with FPU, video display
controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports,
SD and on-chip USB.
The RSK2+SH7269 board uses the SH7269 processor. It is often
referred to as just rsk7269.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/serial_sh.c | 4 | ||||
| -rw-r--r-- | drivers/serial/serial_sh.h | 10 |
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index fcf69ab..13919c6 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -35,6 +35,10 @@ # define SCIF_BASE SCIF4_BASE #elif defined(CONFIG_CONS_SCIF5) # define SCIF_BASE SCIF5_BASE +#elif defined(CONFIG_CONS_SCIF6) +# define SCIF_BASE SCIF6_BASE +#elif defined(CONFIG_CONS_SCIF7) +# define SCIF_BASE SCIF7_BASE #else # error "Default SCIF doesn't set....." #endif diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index de3e102..601da43 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -199,6 +199,16 @@ struct uart_port { # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ # endif # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7269) +# define SCSPTR0 0xe8007020 /* 16 bit SCIF */ +# define SCSPTR1 0xe8007820 /* 16 bit SCIF */ +# define SCSPTR2 0xe8008020 /* 16 bit SCIF */ +# define SCSPTR3 0xe8008820 /* 16 bit SCIF */ +# define SCSPTR4 0xe8009020 /* 16 bit SCIF */ +# define SCSPTR5 0xe8009820 /* 16 bit SCIF */ +# define SCSPTR6 0xe800a020 /* 16 bit SCIF */ +# define SCSPTR7 0xe800a820 /* 16 bit SCIF */ +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_CPU_SH7619) # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ |