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authorFeng Kan <fkan@amcc.com>2009-08-21 10:59:42 -0700
committerStefan Roese <sr@denx.de>2009-08-25 17:41:42 +0200
commit68e74567cf317318df52dbcb2ac170ffc5e7758a (patch)
treef2c36859081242b0c1ed87ef1466e7d9cf413873 /drivers/serial
parenta794f59a75bf9fd4a44f1ad2349cae903c42b89c (diff)
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ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driver
Fix ECC Correction bug where the byte offset location were double flipped causing correction routine to toggle the wrong byte location in the ECC segment. The ndfc_calculate_ecc routine change the order of getting the ECC code. /* The NDFC uses Smart Media (SMC) bytes order */ ecc_code[0] = p[2]; ecc_code[1] = p[1]; ecc_code[2] = p[3]; But in the Correction algorithm when calculating the byte offset location, the s1 is used as the upper part of the address. Which again reverse the order making the final byte offset address location incorrect. byteoffs = (s1 << 0) & 0x80; . . byteoffs |= (s0 >> 4) & 0x08; The order is change to read it in straight and let the correction function to revert it to SMC order. Signed-off-by: Feng Kan <fkan@amcc.com> Acked-by: Victor Gallardo <vgallardo@amcc.com> Acked-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/serial')
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