ENGR00113941 MX233: Make UBOOT v2009.01 work on EVK board

Porting MX233 UBOOT from 1.3.3 to V2009.01. Clear old cfg macro, such as
CFG_HZ. Change MAC address getting source from initial configuration to
On-Chip OTP.

Signed-off-by: Lionel Xu <r63889@freescale.com>

3 files changed, 177 insertions, 0 deletions

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 64882a2..ed56269 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,8 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
 COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
 COBJS-$(CONFIG_USB_TTY) += usbtty.o
+COBJS-$(CONFIG_VCTH_SERIAL) += vcth.o
+COBJS-$(CONFIG_STMP3XXX_DBGUART) += stmp3xxx_dbguart.o
 
 COBJS	:= $(sort $(COBJS-y))
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/serial/stmp3xxx_dbguart.c b/drivers/serial/stmp3xxx_dbguart.c
new file mode 100644
index 0000000..1d24da8
--- /dev/null
+++ b/drivers/serial/stmp3xxx_dbguart.c
@@ -0,0 +1,114 @@
+/*
+ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <common.h>
+
+#ifdef CONFIG_STMP3XXX_DBGUART
+
+#include "stmp3xxx_dbguart.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Set baud rate. The settings are always 8n1:
+ * 8 data bits, no parity, 1 stop bit
+ */
+void serial_setbrg(void)
+{
+	u32 cr, lcr_h;
+	u32 quot;
+
+	/* Disable everything */
+	cr = REG_RD(DBGUART_BASE + UARTDBGCR);
+	REG_WR(DBGUART_BASE + UARTDBGCR, 0);
+
+	/* Calculate and set baudrate */
+	quot = (CONFIG_DBGUART_CLK * 4)	/ gd->baudrate;
+	REG_WR(DBGUART_BASE + UARTDBGFBRD, quot & 0x3f);
+	REG_WR(DBGUART_BASE + UARTDBGIBRD, quot >> 6);
+
+	/* Set 8n1 mode, enable FIFOs */
+	lcr_h = WLEN8 | FEN;
+	REG_WR(DBGUART_BASE + UARTDBGLCR_H, lcr_h);
+
+	/* Enable Debug UART */
+	REG_WR(DBGUART_BASE + UARTDBGCR, cr);
+}
+
+int serial_init(void)
+{
+	u32 cr;
+
+	/* Disable UART */
+	REG_WR(DBGUART_BASE + UARTDBGCR, 0);
+
+	/* Mask interrupts */
+	REG_WR(DBGUART_BASE + UARTDBGIMSC, 0);
+
+	/* Set default baudrate */
+	serial_setbrg();
+
+	/* Enable UART */
+	cr = TXE | RXE | UARTEN;
+	REG_WR(DBGUART_BASE + UARTDBGCR, cr);
+
+	return 0;
+}
+
+/* Send a character */
+void serial_putc(const char c)
+{
+	/* Wait for room in TX FIFO */
+	while (REG_RD(DBGUART_BASE + UARTDBGFR) & TXFF)
+		;
+
+	/* Write the data byte */
+	REG_WR(DBGUART_BASE + UARTDBGDR, c);
+
+	if (c == '\n')
+		serial_putc('\r');
+}
+
+void serial_puts(const char *s)
+{
+	while (*s) {
+		serial_putc(*s++);
+	}
+}
+
+/* Test whether a character is in TX buffer */
+int serial_tstc(void)
+{
+	/* Check if RX FIFO is not empty */
+	return !(REG_RD(DBGUART_BASE + UARTDBGFR) & RXFE);
+}
+
+/* Receive character */
+int serial_getc(void)
+{
+	/* Wait while TX FIFO is empty */
+	while (REG_RD(DBGUART_BASE + UARTDBGFR) & RXFE)
+		;
+
+	/* Read data byte */
+	return REG_RD(DBGUART_BASE + UARTDBGDR) & 0xff;
+}
+
+#endif /* CONFIG_STMP378X_DBGUART */
diff --git a/drivers/serial/stmp3xxx_dbguart.h b/drivers/serial/stmp3xxx_dbguart.h
new file mode 100644
index 0000000..5ad4a85
--- /dev/null
+++ b/drivers/serial/stmp3xxx_dbguart.h
@@ -0,0 +1,61 @@
+/*
+ * Debug UART register definitions
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef STMP3XXX_DBGUART_H
+#define STMP3XXX_DBGUART_H
+
+#include <asm/arch/dbguart.h>
+
+#define UARTDBGDR	0x00
+#define UARTDBGRSR_ECR	0x04
+#define UARTDBGFR	0x18
+#define UARTDBGILPR	0x20
+#define UARTDBGIBRD	0x24
+#define UARTDBGFBRD	0x28
+#define UARTDBGLCR_H	0x2c
+#define UARTDBGCR	0x30
+#define UARTDBGIFLS	0x34
+#define UARTDBGIMSC	0x38
+#define UARTDBGRIS	0x3c
+#define UARTDBGMIS	0x40
+#define UARTDBGICR	0x44
+#define UARTDBGDMACR	0x48
+
+/* UARTDBGFR - Flag Register bits */
+#define CTS	0x0001
+#define DSR	0x0002
+#define DCD	0x0004
+#define BUSY	0x0008
+#define RXFE	0x0010
+#define TXFF	0x0020
+#define RXFF	0x0040
+#define TXFE	0x0080
+#define RI	0x0100
+
+/* UARTDBGLCR_H - Line Control Register bits */
+#define BRK	0x0001
+#define PEN	0x0002
+#define EPS	0x0004
+#define STP2	0x0008
+#define FEN	0x0010
+#define WLEN5	0x0000
+#define WLEN6	0x0020
+#define WLEN7	0x0040
+#define WLEN8	0x0060
+#define SPS	0x0080
+
+/* UARTDBGCR - Control Register bits */
+#define UARTEN	0x0001
+#define LBE	0x0080
+#define TXE	0x0100
+#define RXE	0x0200
+#define DTR	0x0400
+#define RTS	0x0800
+#define OUT1	0x1000
+#define OUT2	0x2000
+#define RTSEN	0x4000
+#define CTSEN	0x8000
+
+#endif /* STMP3XXX_DBGUART_H */