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authorJohn Rigby <john.rigby@linaro.org>2011-04-19 10:42:39 +0000
committerWolfgang Denk <wd@denx.de>2011-05-12 19:09:07 +0200
commit910f1ae3eb05533ac0c7f7fe5b31b50b91f7f0e1 (patch)
tree9ef4f320297799db6bf99aa0ea5d29d2bcf492fb /drivers/serial/serial_pl01x.h
parent264eaa0ea967bac32214b87d60cfc86c8b22cac6 (diff)
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Serial: p1011: new vendor init options
Two new options: CONFIG_PL011_SERIAL_RLCR Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) have separate receive and transmit line control registers. Set this variable to initialize the extra register. CONFIG_PL011_SERIAL_FLUSH_ON_INIT On some platforms (e.g. U8500) U-Boot is loaded by a second stage boot loader that has already initialized the UART. Define this variable to flush the UART at init time. empty fifo on init Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Diffstat (limited to 'drivers/serial/serial_pl01x.h')
-rw-r--r--drivers/serial/serial_pl01x.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h
index b670c24..96ee381 100644
--- a/drivers/serial/serial_pl01x.h
+++ b/drivers/serial/serial_pl01x.h
@@ -43,7 +43,11 @@ struct pl01x_regs {
u32 pl010_lcrl; /* 0x10 Line control register, low byte */
u32 pl010_cr; /* 0x14 Control register */
u32 fr; /* 0x18 Flag register (Read only) */
+#ifdef CONFIG_PL011_SERIAL_RLCR
+ u32 pl011_rlcr; /* 0x1c Receive line control register */
+#else
u32 reserved;
+#endif
u32 ilpr; /* 0x20 IrDA low-power counter register */
u32 pl011_ibrd; /* 0x24 Integer baud rate register */
u32 pl011_fbrd; /* 0x28 Fractional baud rate register */