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authorLinus Walleij <linus.walleij@linaro.org>2011-10-02 11:52:52 +0000
committerWolfgang Denk <wd@denx.de>2011-10-22 00:42:04 +0200
commit96baa4c37695b4dac2bde981f59c38e7af19f2eb (patch)
tree4c9c24511165b0571d8ac9579a982ba03483fd1e /drivers/serial/serial_pl01x.c
parent349e83f071e2bf7bd9fec50377bbdcfb1a143666 (diff)
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serial: pl01x: drain PL01x FIFO before baudrate change
Not draining the FIFO and waiting for the UART to be non-busy before changing baudrate results in crap characters on the console, so let's wait for the FIFO to drain and the last character to be clocked out before we do that. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/serial/serial_pl01x.c')
-rw-r--r--drivers/serial/serial_pl01x.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 7a064ff..ed581ae 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -194,7 +194,17 @@ int serial_tstc (void)
void serial_setbrg (void)
{
+ struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
+
baudrate = gd->baudrate;
+ /*
+ * Flush FIFO and wait for non-busy before changing baudrate to avoid
+ * crap in console
+ */
+ while (!(readl(&regs->fr) & UART_PL01x_FR_TXFE))
+ WATCHDOG_RESET();
+ while (readl(&regs->fr) & UART_PL01x_FR_BUSY)
+ WATCHDOG_RESET();
serial_init();
}