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authorVikas Manocha <vikas.manocha@st.com>2014-11-21 10:34:20 -0800
committerTom Rini <trini@ti.com>2014-12-08 09:35:44 -0500
commit2df810717e8737b9c4a7d2a93b0100fcd7eae84f (patch)
tree8f67fc9aab3b18c3b04de0dfea7fe436b08c4543 /drivers/serial/serial_pl01x.c
parenta7deea691c5e85bdf8bc456dd41d5aadc1e49450 (diff)
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serial: pl01x: fix pl011 baud rate configuration
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which is updated on a single write strobe generated by a UART_LCR_H write. So, to internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H must always be performed at the end. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/serial/serial_pl01x.c')
-rw-r--r--drivers/serial/serial_pl01x.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 1860289..a58ad8a 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -122,6 +122,7 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs,
static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
int clock, int baudrate)
{
+ unsigned int lcr;
switch (type) {
case TYPE_PL010: {
unsigned int divisor;
@@ -175,6 +176,13 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
writel(divider, &regs->pl011_ibrd);
writel(fraction, &regs->pl011_fbrd);
+ /*
+ * Internal update of baud rate register require line
+ * control register write
+ */
+ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
+ writel(lcr, &regs->pl011_lcrh);
+
/* Finally, enable the UART */
writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);