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authorJohn Rigby <john.rigby@linaro.org>2011-04-19 10:42:39 +0000
committerWolfgang Denk <wd@denx.de>2011-05-12 19:09:07 +0200
commit910f1ae3eb05533ac0c7f7fe5b31b50b91f7f0e1 (patch)
tree9ef4f320297799db6bf99aa0ea5d29d2bcf492fb /drivers/serial/serial_pl01x.c
parent264eaa0ea967bac32214b87d60cfc86c8b22cac6 (diff)
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Serial: p1011: new vendor init options
Two new options: CONFIG_PL011_SERIAL_RLCR Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) have separate receive and transmit line control registers. Set this variable to initialize the extra register. CONFIG_PL011_SERIAL_FLUSH_ON_INIT On some platforms (e.g. U8500) U-Boot is loaded by a second stage boot loader that has already initialized the UART. Define this variable to flush the UART at init time. empty fifo on init Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Diffstat (limited to 'drivers/serial/serial_pl01x.c')
-rw-r--r--drivers/serial/serial_pl01x.c30
1 files changed, 27 insertions, 3 deletions
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 5dfcde8..7a064ff 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -111,6 +111,15 @@ int serial_init (void)
unsigned int divider;
unsigned int remainder;
unsigned int fraction;
+ unsigned int lcr;
+
+#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+ /* Empty RX fifo if necessary */
+ if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
+ while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
+ readl(&regs->dr);
+ }
+#endif
/* First, disable everything */
writel(0, &regs->pl011_cr);
@@ -131,9 +140,24 @@ int serial_init (void)
writel(fraction, &regs->pl011_fbrd);
/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
- writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN,
- &regs->pl011_lcrh);
-
+ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
+ writel(lcr, &regs->pl011_lcrh);
+
+#ifdef CONFIG_PL011_SERIAL_RLCR
+ {
+ int i;
+
+ /*
+ * Program receive line control register after waiting
+ * 10 bus cycles. Delay be writing to readonly register
+ * 10 times
+ */
+ for (i = 0; i < 10; i++)
+ writel(lcr, &regs->fr);
+
+ writel(lcr, &regs->pl011_rlcr);
+ }
+#endif
/* Finally, enable the UART */
writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
&regs->pl011_cr);