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authorYe Li <ye.li@nxp.com>2016-03-03 17:23:26 +0800
committerguoyin.chen <guoyin.chen@freescale.com>2016-03-04 15:35:58 +0800
commitc54bd59f57d73309e0e2aab59ec1049cd4bec01a (patch)
tree4c40c2fcbc90815b726611dfb7572d4a6374b477 /drivers/rtc/x1205.c
parent74428d2f0d5ba91383ae1d4420b819c08e64e710 (diff)
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MLK-12488 mx6sl/ul/sx: Fix incorrect clear mmdc_ch0 handshake mask
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'drivers/rtc/x1205.c')
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