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authorDave Liu <daveliu@freescale.com>2007-06-25 10:41:04 +0800
committerKim Phillips <kim.phillips@freescale.com>2007-08-10 01:12:03 -0500
commitff9658d7049bf8c8e8e0a05dbe5e9f7e91aa5a5d (patch)
treeffd9601b7ffc3c88c2839badda84ecb3d43775bc /drivers/qe
parent66dc2c2dc51f8b88bb8e231bc80cd92eae1d6476 (diff)
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mpc83xx: Fix the align bug of SDMA buffer
According to the latest user manual, the SDMA temporary buffer base address must be 4KB aligned. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'drivers/qe')
-rw-r--r--drivers/qe/qe.c2
-rw-r--r--drivers/qe/qe.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 5f20962..0f5232a 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -98,7 +98,7 @@ static void qe_sdma_init(void)
out_be32(&p->sdaqmr, 0);
/* Allocate 2KB temporary buffer for sdma */
- sdma_buffer_base = qe_muram_alloc(2048, 64);
+ sdma_buffer_base = qe_muram_alloc(2048, 4096);
out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
/* Clear sdma status */
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 0bcd0a9..400b1a6 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -29,7 +29,7 @@
#define QE_NUM_OF_BRGS 16
#define UCC_MAX_NUM 8
-#define QE_DATAONLY_BASE (uint)(128)
+#define QE_DATAONLY_BASE 0
#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
/* QE threads SNUM