Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

4 files changed, 109 insertions, 29 deletions

diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 344c649..ed7ed65 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -34,12 +34,12 @@
 #ifdef CONFIG_UEC_ETH1
 static uec_info_t eth1_uec_info = {
 	.uf_info		= {
-		.ucc_num	= CFG_UEC1_UCC_NUM,
-		.rx_clock	= CFG_UEC1_RX_CLK,
-		.tx_clock	= CFG_UEC1_TX_CLK,
-		.eth_type	= CFG_UEC1_ETH_TYPE,
+		.ucc_num	= CONFIG_SYS_UEC1_UCC_NUM,
+		.rx_clock	= CONFIG_SYS_UEC1_RX_CLK,
+		.tx_clock	= CONFIG_SYS_UEC1_TX_CLK,
+		.eth_type	= CONFIG_SYS_UEC1_ETH_TYPE,
 	},
-#if (CFG_UEC1_ETH_TYPE == FAST_ETH)
+#if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
 	.num_threads_tx		= UEC_NUM_OF_THREADS_1,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_1,
 #else
@@ -50,19 +50,19 @@ static uec_info_t eth1_uec_info = {
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
-	.phy_address		= CFG_UEC1_PHY_ADDR,
-	.enet_interface		= CFG_UEC1_INTERFACE_MODE,
+	.phy_address		= CONFIG_SYS_UEC1_PHY_ADDR,
+	.enet_interface		= CONFIG_SYS_UEC1_INTERFACE_MODE,
 };
 #endif
 #ifdef CONFIG_UEC_ETH2
 static uec_info_t eth2_uec_info = {
 	.uf_info		= {
-		.ucc_num	= CFG_UEC2_UCC_NUM,
-		.rx_clock	= CFG_UEC2_RX_CLK,
-		.tx_clock	= CFG_UEC2_TX_CLK,
-		.eth_type	= CFG_UEC2_ETH_TYPE,
+		.ucc_num	= CONFIG_SYS_UEC2_UCC_NUM,
+		.rx_clock	= CONFIG_SYS_UEC2_RX_CLK,
+		.tx_clock	= CONFIG_SYS_UEC2_TX_CLK,
+		.eth_type	= CONFIG_SYS_UEC2_ETH_TYPE,
 	},
-#if (CFG_UEC2_ETH_TYPE == FAST_ETH)
+#if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
 	.num_threads_tx		= UEC_NUM_OF_THREADS_1,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_1,
 #else
@@ -73,19 +73,19 @@ static uec_info_t eth2_uec_info = {
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
-	.phy_address		= CFG_UEC2_PHY_ADDR,
-	.enet_interface		= CFG_UEC2_INTERFACE_MODE,
+	.phy_address		= CONFIG_SYS_UEC2_PHY_ADDR,
+	.enet_interface		= CONFIG_SYS_UEC2_INTERFACE_MODE,
 };
 #endif
 #ifdef CONFIG_UEC_ETH3
 static uec_info_t eth3_uec_info = {
 	.uf_info		= {
-		.ucc_num	= CFG_UEC3_UCC_NUM,
-		.rx_clock	= CFG_UEC3_RX_CLK,
-		.tx_clock	= CFG_UEC3_TX_CLK,
-		.eth_type	= CFG_UEC3_ETH_TYPE,
+		.ucc_num	= CONFIG_SYS_UEC3_UCC_NUM,
+		.rx_clock	= CONFIG_SYS_UEC3_RX_CLK,
+		.tx_clock	= CONFIG_SYS_UEC3_TX_CLK,
+		.eth_type	= CONFIG_SYS_UEC3_ETH_TYPE,
 	},
-#if (CFG_UEC3_ETH_TYPE == FAST_ETH)
+#if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH)
 	.num_threads_tx		= UEC_NUM_OF_THREADS_1,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_1,
 #else
@@ -96,19 +96,19 @@ static uec_info_t eth3_uec_info = {
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
-	.phy_address		= CFG_UEC3_PHY_ADDR,
-	.enet_interface		= CFG_UEC3_INTERFACE_MODE,
+	.phy_address		= CONFIG_SYS_UEC3_PHY_ADDR,
+	.enet_interface		= CONFIG_SYS_UEC3_INTERFACE_MODE,
 };
 #endif
 #ifdef CONFIG_UEC_ETH4
 static uec_info_t eth4_uec_info = {
 	.uf_info		= {
-		.ucc_num	= CFG_UEC4_UCC_NUM,
-		.rx_clock	= CFG_UEC4_RX_CLK,
-		.tx_clock	= CFG_UEC4_TX_CLK,
-		.eth_type	= CFG_UEC4_ETH_TYPE,
+		.ucc_num	= CONFIG_SYS_UEC4_UCC_NUM,
+		.rx_clock	= CONFIG_SYS_UEC4_RX_CLK,
+		.tx_clock	= CONFIG_SYS_UEC4_TX_CLK,
+		.eth_type	= CONFIG_SYS_UEC4_ETH_TYPE,
 	},
-#if (CFG_UEC4_ETH_TYPE == FAST_ETH)
+#if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH)
 	.num_threads_tx		= UEC_NUM_OF_THREADS_1,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_1,
 #else
@@ -119,12 +119,58 @@ static uec_info_t eth4_uec_info = {
 	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
-	.phy_address		= CFG_UEC4_PHY_ADDR,
-	.enet_interface		= CFG_UEC4_INTERFACE_MODE,
+	.phy_address		= CONFIG_SYS_UEC4_PHY_ADDR,
+	.enet_interface		= CONFIG_SYS_UEC4_INTERFACE_MODE,
+};
+#endif
+#ifdef CONFIG_UEC_ETH5
+static uec_info_t eth5_uec_info = {
+	.uf_info		= {
+		.ucc_num	= CONFIG_SYS_UEC5_UCC_NUM,
+		.rx_clock	= CONFIG_SYS_UEC5_RX_CLK,
+		.tx_clock	= CONFIG_SYS_UEC5_TX_CLK,
+		.eth_type	= CONFIG_SYS_UEC5_ETH_TYPE,
+	},
+#if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH)
+	.num_threads_tx		= UEC_NUM_OF_THREADS_1,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_1,
+#else
+	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
+#endif
+	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.tx_bd_ring_len		= 16,
+	.rx_bd_ring_len		= 16,
+	.phy_address		= CONFIG_SYS_UEC5_PHY_ADDR,
+	.enet_interface		= CONFIG_SYS_UEC5_INTERFACE_MODE,
+};
+#endif
+#ifdef CONFIG_UEC_ETH6
+static uec_info_t eth6_uec_info = {
+	.uf_info		= {
+		.ucc_num	= CONFIG_SYS_UEC6_UCC_NUM,
+		.rx_clock	= CONFIG_SYS_UEC6_RX_CLK,
+		.tx_clock	= CONFIG_SYS_UEC6_TX_CLK,
+		.eth_type	= CONFIG_SYS_UEC6_ETH_TYPE,
+	},
+#if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH)
+	.num_threads_tx		= UEC_NUM_OF_THREADS_1,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_1,
+#else
+	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
+#endif
+	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.tx_bd_ring_len		= 16,
+	.rx_bd_ring_len		= 16,
+	.phy_address		= CONFIG_SYS_UEC6_PHY_ADDR,
+	.enet_interface		= CONFIG_SYS_UEC6_INTERFACE_MODE,
 };
 #endif
 
-#define MAXCONTROLLERS	(4)
+#define MAXCONTROLLERS	(6)
 
 static struct eth_device *devlist[MAXCONTROLLERS];
 
@@ -424,6 +470,7 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
 			upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 			break;
 		case ENET_1000_RGMII_RXID:
+		case ENET_1000_RGMII_ID:
 		case ENET_1000_RGMII:
 			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 			upsmr |= UPSMR_RPM;
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index e357a92..0b64499 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -642,6 +642,7 @@ typedef enum enet_interface {
 	ENET_100_RGMII,
 	ENET_1000_GMII,
 	ENET_1000_RGMII,
+	ENET_1000_RGMII_ID,
 	ENET_1000_RGMII_RXID,
 	ENET_1000_TBI,
 	ENET_1000_RTBI
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 186922e..2243d3b 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -376,6 +376,29 @@ static int bcm_init(struct uec_mii_info *mii_info)
 	 return 0;
 }
 
+static int marvell_init(struct uec_mii_info *mii_info)
+{
+	struct eth_device *edev = mii_info->dev;
+	uec_private_t *uec = edev->priv;
+
+	if (uec->uec_info->enet_interface == ENET_1000_RGMII_ID) {
+		int temp;
+
+		temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
+		temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
+		phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
+
+		temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);
+		temp &= ~MII_M1111_HWCFG_MODE_MASK;
+		temp |= MII_M1111_HWCFG_MODE_RGMII;
+		phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
+
+		phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
+	}
+
+	return 0;
+}
+
 static int marvell_read_status (struct uec_mii_info *mii_info)
 {
 	u16 status;
@@ -538,6 +561,7 @@ static struct phy_info phy_info_marvell = {
 	.phy_id_mask = 0xffffff00,
 	.name = "Marvell 88E11x1",
 	.features = MII_GBIT_FEATURES,
+	.init = &marvell_init,
 	.config_aneg = &marvell_config_aneg,
 	.read_status = &marvell_read_status,
 	.ack_interrupt = &marvell_ack_interrupt,
diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index 6f769fb..7ac1ff9 100644
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h
@@ -77,6 +77,14 @@
 #define MII_M1011_IMASK_INIT		0x6400
 #define MII_M1011_IMASK_CLEAR		0x0000
 
+/* 88E1111 PHY Register */
+#define MII_M1111_PHY_EXT_CR            0x14
+#define MII_M1111_RX_DELAY              0x80
+#define MII_M1111_TX_DELAY              0x2
+#define MII_M1111_PHY_EXT_SR            0x1b
+#define MII_M1111_HWCFG_MODE_MASK       0xf
+#define MII_M1111_HWCFG_MODE_RGMII      0xb
+
 #define MII_DM9161_SCR			0x10
 #define MII_DM9161_SCR_INIT		0x0610
 #define MII_DM9161_SCR_RMII_INIT	0x0710