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authorHaiying Wang <Haiying.Wang@freescale.com>2009-05-21 15:34:14 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-06-12 17:16:59 -0500
commit7211fbfa18f3061858696150ee6e9e093d9eceae (patch)
tree6be78918f7bc3679ab9327b4859812eafae342ff /drivers/qe/uec.c
parentb3d7f20f43a0f8d11c65e2f92153b5512b11580c (diff)
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drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and define MAX_QE_RISC for QE based silicons. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/qe/uec.c')
-rw-r--r--drivers/qe/uec.c32
1 files changed, 31 insertions, 1 deletions
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index e67c0ba..d02c8c9 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC4_PHY_ADDR,
@@ -138,8 +158,13 @@ static uec_info_t eth5_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC5_PHY_ADDR,
@@ -161,8 +186,13 @@ static uec_info_t eth6_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC6_PHY_ADDR,