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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-05-21 15:34:14 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 17:16:59 -0500 |
| commit | 7211fbfa18f3061858696150ee6e9e093d9eceae (patch) | |
| tree | 6be78918f7bc3679ab9327b4859812eafae342ff /drivers/qe/qe.h | |
| parent | b3d7f20f43a0f8d11c65e2f92153b5512b11580c (diff) | |
| download | u-boot-imx-7211fbfa18f3061858696150ee6e9e093d9eceae.zip u-boot-imx-7211fbfa18f3061858696150ee6e9e093d9eceae.tar.gz u-boot-imx-7211fbfa18f3061858696150ee6e9e093d9eceae.tar.bz2 | |
drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/qe/qe.h')
| -rw-r--r-- | drivers/qe/qe.h | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index d78edba..2128f56 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * Dave Liu <daveliu@freescale.com> * based on source code of Shlomi Gridish @@ -46,11 +46,16 @@ typedef struct qe_snum { /* QE RISC allocation */ -typedef enum qe_risc_allocation { - QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ - QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ - QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */ -} qe_risc_allocation_e; +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2) +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2 | \ + QE_RISC_ALLOCATION_RISC3 | \ + QE_RISC_ALLOCATION_RISC4) /* QE CECR commands for UCC fast. */ |