summaryrefslogtreecommitdiff
path: root/drivers/pinctrl/uniphier/pinctrl-uniphier.h
diff options
context:
space:
mode:
authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-03-24 22:32:44 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2016-04-01 00:54:00 +0900
commit8cc92b996ddecd4c364d0bbb474c3569ebec55c7 (patch)
tree6a726da2b75e7e8f4a495519c19fde6a6c3ecdbb /drivers/pinctrl/uniphier/pinctrl-uniphier.h
parent510454db045143e374a7d64e6bb043799d0023d7 (diff)
downloadu-boot-imx-8cc92b996ddecd4c364d0bbb474c3569ebec55c7.zip
u-boot-imx-8cc92b996ddecd4c364d0bbb474c3569ebec55c7.tar.gz
u-boot-imx-8cc92b996ddecd4c364d0bbb474c3569ebec55c7.tar.bz2
pinctrl: uniphier: introduce capability flag
The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding new ones. Having flags would be better than adding new members every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'drivers/pinctrl/uniphier/pinctrl-uniphier.h')
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 6bdebf2..d582317 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -7,6 +7,7 @@
#ifndef __PINCTRL_UNIPHIER_H__
#define __PINCTRL_UNIPHIER_H__
+#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/types.h>
@@ -59,8 +60,7 @@ struct uniphier_pinctrl_group {
* @functions_count: number of pinmux functions
* @mux_bits: bit width of each pinmux register
* @reg_stride: stride of pinmux register address
- * @load_pinctrl: if true, LOAD_PINMUX register must be set to one for new
- * values in pinmux registers to become really effective
+ * @caps: SoC-specific capability flag
*/
struct uniphier_pinctrl_socdata {
const struct uniphier_pinctrl_pin *pins;
@@ -69,9 +69,8 @@ struct uniphier_pinctrl_socdata {
int groups_count;
const char * const *functions;
int functions_count;
- unsigned mux_bits;
- unsigned reg_stride;
- bool load_pinctrl;
+ unsigned caps;
+#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
};
#define UNIPHIER_PINCTRL_PIN(a, b) \