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authorGabor Juhos <juhosg@openwrt.org>2013-06-13 12:59:35 +0200
committerTom Rini <trini@ti.com>2013-07-24 09:51:07 -0400
commitee8b1e29597bcf18bfebd6fd8eccc8e245046352 (patch)
tree0bc3e953a2bf45c34e985dd7a8714a674c3ce440 /drivers/pci
parentc325916563ac67ec5f86748060c2909a9b960bee (diff)
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MIPS: mips32/cache.S: store cache line size in t8 register
Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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