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author | Ye.Li <B37916@freescale.com> | 2014-09-09 16:20:56 +0800 |
---|---|---|
committer | Ye.Li <B37916@freescale.com> | 2014-09-10 09:49:30 +0800 |
commit | e36a66415f63621417c7fa1c7865ef5b56dca547 (patch) | |
tree | 00a2eab2006c1ada9396aba5afaf93c9730d701f /drivers/pci | |
parent | aa76a7e472e34bc59554f9932d611b1047d24590 (diff) | |
download | u-boot-imx-e36a66415f63621417c7fa1c7865ef5b56dca547.zip u-boot-imx-e36a66415f63621417c7fa1c7865ef5b56dca547.tar.gz u-boot-imx-e36a66415f63621417c7fa1c7865ef5b56dca547.tar.bz2 |
ENGR00330792 imx: mx6: Merge anatop registers to CCM structure
THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/pcie_imx.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 0b5b886..9f3e604 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -103,6 +103,7 @@ static void print_regs(int contain_pcie_reg) #else struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_GPR_BASE_ADDR; #endif + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; val = readl(&iomuxc_regs->gpr[1]); DBGF("GPR01 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[1], val); val = readl(&iomuxc_regs->gpr[5]); @@ -111,10 +112,10 @@ static void print_regs(int contain_pcie_reg) DBGF("GPR08 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[8], val); val = readl(&iomuxc_regs->gpr[12]); DBGF("GPR12 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[12], val); - val = readl(ANATOP_BASE_ADDR + 0xe0); - DBGF("PLL06 a:0x%08x v:0x%08x\n", ANATOP_BASE_ADDR + 0xe0, val); - val = readl(ANATOP_BASE_ADDR + 0x160); - DBGF("MISC1 a:0x%08x v:0x%08x\n", ANATOP_BASE_ADDR + 0x160, val); + val = readl(&ccm_regs->analog_pll_enet); + DBGF("PLL06 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->analog_pll_enet, val); + val = readl(&ccm_regs->ana_misc1); + DBGF("MISC1 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->ana_misc1, val); if (contain_pcie_reg) { val = readl(MX6_DBI_ADDR + 0x728); DBGF("dbr0 offset 0x728 %08x\n", val); |