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| author | Liu Gang <Gang.Liu@freescale.com> | 2012-10-14 20:55:17 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 15:52:46 -0500 |
| commit | 19e4a00965f03d5d64af00b7b4258dff43e57d17 (patch) | |
| tree | 3f796e643b234fc61637d1b0163efa5a27f34153 /drivers/pci | |
| parent | d8812bdbba21eefdf773ab3a42dcdf966d68ab92 (diff) | |
| download | u-boot-imx-19e4a00965f03d5d64af00b7b4258dff43e57d17.zip u-boot-imx-19e4a00965f03d5d64af00b7b4258dff43e57d17.tar.gz u-boot-imx-19e4a00965f03d5d64af00b7b4258dff43e57d17.tar.bz2 | |
powerpc/boot: Change the compile macro for SRIO & PCIE boot master module
Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.
So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/fsl_pci_init.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index e8eb9d6..48ae163 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, return 1; } -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER static void fsl_pcie_boot_master(pit_t *pi) { /* configure inbound window for slave's u-boot image */ @@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* see if we are a PCIe or PCI controller */ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER /* boot from PCIE --master */ char *s = getenv("bootmaster"); char pcie[6]; @@ -602,7 +602,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, if (fsl_is_pci_agent(hose)) { fsl_pci_config_unlock(hose); hose->last_busno = hose->first_busno; -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER } else { /* boot from PCIE --master releases slave's core 0 */ char *s = getenv("bootmaster"); |