diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2011-02-04 09:00:43 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-04 09:24:41 -0500 |
| commit | b6ccd2c9dee758a70e761403a41e60c31a1cfcec (patch) | |
| tree | c47fc0dc31ba8bf0f837eea05d0eebd48449cc4e /drivers/pci | |
| parent | 24995d829aecc6abca0f1b41443ae0cd9b4fde5a (diff) | |
| download | u-boot-imx-b6ccd2c9dee758a70e761403a41e60c31a1cfcec.zip u-boot-imx-b6ccd2c9dee758a70e761403a41e60c31a1cfcec.tar.gz u-boot-imx-b6ccd2c9dee758a70e761403a41e60c31a1cfcec.tar.bz2 | |
fsl_pci: Add support for FSL PCIe controllers v2.x
FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.x
Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status register
Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.
To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/fsl_pci_init.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index dc34bd6..ab461b4 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -223,6 +223,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; u16 temp16; u32 temp32; + u32 block_rev; int enabled, r, inbound = 0; u16 ltssm; u8 temp8, pcie_cap; @@ -232,13 +233,20 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* Initialize ATMU registers based on hose regions and flags */ volatile pot_t *po = &pci->pot[1]; /* skip 0 */ - volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */ + volatile pit_t *pi; u64 out_hi = 0, out_lo = -1ULL; u32 pcicsrbar, pcicsrbar_sz; pci_setup_indirect(hose, cfg_addr, cfg_data); + block_rev = in_be32(&pci->block_rev1); + if (PEX_IP_BLK_REV_2_2 <= block_rev) { + pi = &pci->pit[2]; /* 0xDC0 */ + } else { + pi = &pci->pit[3]; /* 0xDE0 */ + } + /* Handle setup of outbound windows first */ for (r = 0; r < hose->region_count; r++) { unsigned long flags = hose->regions[r].flags; |