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authorTom Rini <trini@konsulko.com>2016-07-26 18:33:04 -0400
committerTom Rini <trini@konsulko.com>2016-07-26 18:33:04 -0400
commit0b6699ad8ea95803d7ce40d1dc1caea902a6d22c (patch)
tree56dff240daa78cd0bb10233d4863691be3590504 /drivers/net
parent4fd92db8dbf6d9275a921e8e9f2b6aeeba7e5002 (diff)
parent2eb1ff3b5b61352dcf43ca48f2b6470ec312b8d7 (diff)
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Merge branch 'master' of http://git.denx.de/u-boot-sunxi
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/sun8i_emac.c13
1 files changed, 1 insertions, 12 deletions
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 4bed50d..7c088c3 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -22,10 +22,6 @@
#include <miiphy.h>
#include <net.h>
-#define SCTL_EMAC_TX_CLK_SRC_MII BIT(0)
-#define SCTL_EMAC_EPIT_MII BIT(2)
-#define SCTL_EMAC_CLK_SEL BIT(18) /* 25 Mhz */
-
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
@@ -589,9 +585,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
/* Set clock gating for ephy */
setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
- /* Set Tx clock source as MII with rate 25 MZ */
- setbits_le32(priv->sysctl_reg, SCTL_EMAC_TX_CLK_SRC_MII |
- SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL);
/* Deassert EPHY */
setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
}
@@ -599,9 +592,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
/* Set clock gating for emac */
setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
- /* Set EMAC clock */
- setbits_le32(&ccm->axi_gate, (BIT(1) | BIT(0)));
-
/* De-assert EMAC */
setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
}
@@ -696,12 +686,11 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
priv->mac_reg = (void *)pdata->iobase;
sun8i_emac_board_setup(priv);
+ sun8i_emac_set_syscon(priv);
sun8i_mdio_init(dev->name, priv);
priv->bus = miiphy_get_dev_by_name(dev->name);
- sun8i_emac_set_syscon(priv);
-
return sun8i_phy_init(priv, dev);
}