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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-08-26 06:17:27 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-08-26 07:54:01 -0700 |
| commit | 1d8a078b29433f35608cd0fbd94d0feed3bfb33d (patch) | |
| tree | 20f3069aa657a47c3d4649e71a471feebbe31328 /drivers/net | |
| parent | 7d31c6ab83d8a5875875eda041c0a1e756189917 (diff) | |
| download | u-boot-imx-1d8a078b29433f35608cd0fbd94d0feed3bfb33d.zip u-boot-imx-1d8a078b29433f35608cd0fbd94d0feed3bfb33d.tar.gz u-boot-imx-1d8a078b29433f35608cd0fbd94d0feed3bfb33d.tar.bz2 | |
net: e1000: Fix build warnings for 32-bit
commit 6497e37 "net: e1000: Support 64-bit physical address" causes
compiler warnings on 32-bit U-Boot build below.
drivers/net/e1000.c: In function 'e1000_configure_tx':
drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default]
drivers/net/e1000.c: In function 'e1000_configure_rx':
drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default]
This commit fixes the build warnings.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/e1000.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 6f74d30..7b830ff 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -4978,8 +4978,8 @@ e1000_configure_tx(struct e1000_hw *hw) unsigned long tipg, tarc; uint32_t ipgr1, ipgr2; - E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base & 0xffffffff); - E1000_WRITE_REG(hw, TDBAH, (unsigned long)tx_base >> 32); + E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base)); + E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base)); E1000_WRITE_REG(hw, TDLEN, 128); @@ -5103,6 +5103,7 @@ e1000_configure_rx(struct e1000_hw *hw) { unsigned long rctl, ctrl_ext; rx_tail = 0; + /* make sure receives are disabled while setting up the descriptors */ rctl = E1000_READ_REG(hw, RCTL); E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); @@ -5122,8 +5123,8 @@ e1000_configure_rx(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); } /* Setup the Base and Length of the Rx Descriptor Ring */ - E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base & 0xffffffff); - E1000_WRITE_REG(hw, RDBAH, (unsigned long)rx_base >> 32); + E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base)); + E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base)); E1000_WRITE_REG(hw, RDLEN, 128); |