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authorTom Rini <trini@ti.com>2013-08-18 14:14:34 -0400
committerTom Rini <trini@ti.com>2013-08-18 14:14:34 -0400
commite20cc2ca15b5b0644f51b6e58d530d70acd2bc00 (patch)
treef85a22536682ef54e77b1ba95cf0b71d00644632 /drivers/net
parentf21876174364391757e743cb8673d3fc5fce7ac7 (diff)
parent9ed887caecb9ecb0c68773a1870d143b9f28d3da (diff)
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Merge branch 'master' of git://88.191.163.10/u-boot-arm
Fixup an easy conflict over adding the clk_get prototype and USB_OTG defines for am33xx having moved. Conflicts: arch/arm/include/asm/arch-am33xx/hardware.h Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/calxedaxgmac.c2
-rw-r--r--drivers/net/cpsw.c7
-rw-r--r--drivers/net/phy/phy.c6
3 files changed, 9 insertions, 6 deletions
diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c
index 2c61710..ff94865 100644
--- a/drivers/net/calxedaxgmac.c
+++ b/drivers/net/calxedaxgmac.c
@@ -390,7 +390,7 @@ static int xgmac_init(struct eth_device *dev, bd_t * bis)
/* set flow control parameters and store and forward mode */
value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
(FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
- XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF | XGMAC_CORE_OMR_RSF;
+ XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF;
writel(value, &regs->core_opmode);
/* enable pause frames */
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 379b679..9bab71a 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -51,8 +51,6 @@
#define CPDMA_RXCP_VER1 0x160
#define CPDMA_RXCP_VER2 0x260
-#define CPDMA_RAM_ADDR 0x4a102000
-
/* Descriptor mode bits */
#define CPDMA_DESC_SOP BIT(31)
#define CPDMA_DESC_EOP BIT(30)
@@ -489,7 +487,7 @@ static inline void wait_for_idle(void)
static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
int dev_addr, int phy_reg)
{
- unsigned short data;
+ int data;
u32 reg;
if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
@@ -774,6 +772,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis)
/* enable statistics collection only on the host port */
__raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
+ __raw_writel(0x7, &priv->regs->stat_port_en);
cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
@@ -984,12 +983,12 @@ int cpsw_register(struct cpsw_platform_data *data)
return -ENOMEM;
}
- priv->descs = (void *)CPDMA_RAM_ADDR;
priv->host_port = data->host_port_num;
priv->regs = regs;
priv->host_port_regs = regs + data->host_port_reg_ofs;
priv->dma_regs = regs + data->cpdma_reg_ofs;
priv->ale_regs = regs + data->ale_reg_ofs;
+ priv->descs = (void *)regs + data->bd_ram_ofs;
int idx = 0;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 6fe793d..62925bb 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -277,7 +277,7 @@ int genphy_parse_link(struct phy_device *phydev)
/* We're using autonegotiation */
if (mii_reg & BMSR_ANEGCAPABLE) {
u32 lpa = 0;
- u32 gblpa = 0;
+ int gblpa = 0;
u32 estatus = 0;
/* Check for gigabit capability */
@@ -286,6 +286,10 @@ int genphy_parse_link(struct phy_device *phydev)
* both PHYs in the link
*/
gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
+ if (gblpa < 0) {
+ debug("Could not read MII_STAT1000. Ignoring gigabit capability\n");
+ gblpa = 0;
+ }
gblpa &= phy_read(phydev,
MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
}