Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

49 files changed, 4722 insertions, 1568 deletions

diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
new file mode 100644
index 0000000..1978269
--- /dev/null
+++ b/drivers/net/4xx_enet.c
@@ -0,0 +1,2126 @@
+/*-----------------------------------------------------------------------------+
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------+
+ *
+ *  File Name:	enetemac.c
+ *
+ *  Function:	Device driver for the ethernet EMAC3 macro on the 405GP.
+ *
+ *  Author:	Mark Wisner
+ *
+ *  Change Activity-
+ *
+ *  Date	Description of Change					    BY
+ *  ---------	---------------------					    ---
+ *  05-May-99	Created							    MKW
+ *  27-Jun-99	Clean up						    JWB
+ *  16-Jul-99	Added MAL error recovery and better IP packet handling	    MKW
+ *  29-Jul-99	Added Full duplex support				    MKW
+ *  06-Aug-99	Changed names for Mal CR reg				    MKW
+ *  23-Aug-99	Turned off SYE when running at 10Mbs			    MKW
+ *  24-Aug-99	Marked descriptor empty after call_xlc			    MKW
+ *  07-Sep-99	Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16	    MCG
+ *		to avoid chaining maximum sized packets. Push starting
+ *		RX descriptor address up to the next cache line boundary.
+ *  16-Jan-00	Added support for booting with IP of 0x0		    MKW
+ *  15-Mar-00	Updated enetInit() to enable broadcast addresses in the
+ *		EMAC_RXM register.					    JWB
+ *  12-Mar-01	anne-sophie.harnois@nextream.fr
+ *		 - Variables are compatible with those already defined in
+ *		  include/net.h
+ *		- Receive buffer descriptor ring is used to send buffers
+ *		  to the user
+ *		- Info print about send/received/handled packet number if
+ *		  INFO_405_ENET is set
+ *  17-Apr-01	stefan.roese@esd-electronics.com
+ *		- MAL reset in "eth_halt" included
+ *		- Enet speed and duplex output now in one line
+ *  08-May-01	stefan.roese@esd-electronics.com
+ *		- MAL error handling added (eth_init called again)
+ *  13-Nov-01	stefan.roese@esd-electronics.com
+ *		- Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
+ *  04-Jan-02	stefan.roese@esd-electronics.com
+ *		- Wait for PHY auto negotiation to complete added
+ *  06-Feb-02	stefan.roese@esd-electronics.com
+ *		- Bug fixed in waiting for auto negotiation to complete
+ *  26-Feb-02	stefan.roese@esd-electronics.com
+ *		- rx and tx buffer descriptors now allocated (no fixed address
+ *		  used anymore)
+ *  17-Jun-02	stefan.roese@esd-electronics.com
+ *		- MAL error debug printf 'M' removed (rx de interrupt may
+ *		  occur upon many incoming packets with only 4 rx buffers).
+ *-----------------------------------------------------------------------------*
+ *  17-Nov-03	travis.sawyer@sandburst.com
+ *		- ported from 405gp_enet.c to utilized upto 4 EMAC ports
+ *		  in the 440GX.	 This port should work with the 440GP
+ *		  (2 EMACs) also
+ *  15-Aug-05	sr@denx.de
+ *		- merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
+		  now handling all 4xx cpu's.
+ *-----------------------------------------------------------------------------*/
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <commproc.h>
+#include <ppc4xx.h>
+#include <ppc4xx_enet.h>
+#include <405_mal.h>
+#include <miiphy.h>
+#include <malloc.h>
+
+#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
+#error "CONFIG_MII has to be defined!"
+#endif
+
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
+#error "CONFIG_NET_MULTI has to be defined for NetConsole"
+#endif
+
+#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
+#define PHY_AUTONEGOTIATE_TIMEOUT 5000	/* 5000 ms autonegotiate timeout */
+
+/* Ethernet Transmit and Receive Buffers */
+/* AS.HARNOIS
+ * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
+ * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
+ */
+#define ENET_MAX_MTU	       PKTSIZE
+#define ENET_MAX_MTU_ALIGNED   PKTSIZE_ALIGN
+
+/*-----------------------------------------------------------------------------+
+ * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
+ * Interrupt Controller).
+ *-----------------------------------------------------------------------------*/
+#define ETH_IRQ_NUM(dev)	(VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
+
+#if defined(CONFIG_HAS_ETH3)
+#if !defined(CONFIG_440GX)
+#define UIC_ETHx	(UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
+			 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
+#else
+/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
+#define UIC_ETHx	(UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
+#define UIC_ETHxB	(UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
+#endif /* !defined(CONFIG_440GX) */
+#elif defined(CONFIG_HAS_ETH2)
+#define UIC_ETHx	(UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
+			 UIC_MASK(ETH_IRQ_NUM(2)))
+#elif defined(CONFIG_HAS_ETH1)
+#define UIC_ETHx	(UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
+#else
+#define UIC_ETHx	UIC_MASK(ETH_IRQ_NUM(0))
+#endif
+
+/*
+ * Define a default version for UIC_ETHxB for non 440GX so that we can
+ * use common code for all 4xx variants
+ */
+#if !defined(UIC_ETHxB)
+#define UIC_ETHxB	0
+#endif
+
+#define UIC_MAL_SERR	UIC_MASK(VECNUM_MAL_SERR)
+#define UIC_MAL_TXDE	UIC_MASK(VECNUM_MAL_TXDE)
+#define UIC_MAL_RXDE	UIC_MASK(VECNUM_MAL_RXDE)
+#define UIC_MAL_TXEOB	UIC_MASK(VECNUM_MAL_TXEOB)
+#define UIC_MAL_RXEOB	UIC_MASK(VECNUM_MAL_RXEOB)
+
+#define MAL_UIC_ERR	(UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
+#define MAL_UIC_DEF	(UIC_MAL_RXEOB | MAL_UIC_ERR)
+
+/*
+ * We have 3 different interrupt types:
+ * - MAL interrupts indicating successful transfer
+ * - MAL error interrupts indicating MAL related errors
+ * - EMAC interrupts indicating EMAC related errors
+ *
+ * All those interrupts can be on different UIC's, but since
+ * now at least all interrupts from one type are on the same
+ * UIC. Only exception is 440GX where the EMAC interrupts are
+ * spread over two UIC's!
+ */
+#if defined(CONFIG_440GX)
+#define UIC_BASE_MAL	UIC1_DCR_BASE
+#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
+#define UIC_BASE_EMAC	UIC2_DCR_BASE
+#define UIC_BASE_EMAC_B	UIC3_DCR_BASE
+#else
+#define UIC_BASE_MAL	(UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
+#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
+#define UIC_BASE_EMAC	(UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
+#define UIC_BASE_EMAC_B	(UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
+#endif
+
+#undef INFO_4XX_ENET
+
+#define BI_PHYMODE_NONE	 0
+#define BI_PHYMODE_ZMII	 1
+#define BI_PHYMODE_RGMII 2
+#define BI_PHYMODE_GMII  3
+#define BI_PHYMODE_RTBI  4
+#define BI_PHYMODE_TBI   5
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+#define BI_PHYMODE_SMII  6
+#define BI_PHYMODE_MII   7
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define BI_PHYMODE_RMII  8
+#endif
+#endif
+#define BI_PHYMODE_SGMII 9
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+#define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define SDR0_ETH_CFG_CLK_SEL_V(n)	(0x01 << (8 + n))
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define MAL_RX_CHAN_MUL	8	/* 460EX/GT uses MAL channel 8 for EMAC1 */
+#else
+#define MAL_RX_CHAN_MUL	1
+#endif
+
+/*--------------------------------------------------------------------+
+ * Fixed PHY (PHY-less) support for Ethernet Ports.
+ *--------------------------------------------------------------------*/
+
+/*
+ * Some boards do not have a PHY for each ethernet port. These ports
+ * are known as Fixed PHY (or PHY-less) ports. For such ports, set
+ * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
+ * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
+ * duplex should be for these ports in the board configuration
+ * file.
+ *
+ * For Example:
+ *     #define CONFIG_FIXED_PHY   0xFFFFFFFF
+ *
+ *     #define CONFIG_PHY_ADDR    CONFIG_FIXED_PHY
+ *     #define CONFIG_PHY1_ADDR   1
+ *     #define CONFIG_PHY2_ADDR   CONFIG_FIXED_PHY
+ *     #define CONFIG_PHY3_ADDR   3
+ *
+ *     #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
+ *                     {devnum, speed, duplex},
+ *
+ *     #define CONFIG_SYS_FIXED_PHY_PORTS \
+ *                     CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
+ *                     CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
+ */
+
+#ifndef CONFIG_FIXED_PHY
+#define CONFIG_FIXED_PHY	0xFFFFFFFF /* Fixed PHY (PHY-less) */
+#endif
+
+#ifndef CONFIG_SYS_FIXED_PHY_PORTS
+#define CONFIG_SYS_FIXED_PHY_PORTS	/* default is an empty array */
+#endif
+
+struct fixed_phy_port {
+	unsigned int devnum;	/* ethernet port */
+	unsigned int speed;	/* specified speed 10,100 or 1000 */
+	unsigned int duplex;	/* specified duplex FULL or HALF */
+};
+
+static const struct fixed_phy_port fixed_phy_port[] = {
+	CONFIG_SYS_FIXED_PHY_PORTS	/* defined in board configuration file */
+};
+
+/*-----------------------------------------------------------------------------+
+ * Global variables. TX and RX descriptors and buffers.
+ *-----------------------------------------------------------------------------*/
+#if !defined(CONFIG_NET_MULTI)
+struct eth_device *emac0_dev = NULL;
+#endif
+
+/*
+ * Get count of EMAC devices (doesn't have to be the max. possible number
+ * supported by the cpu)
+ *
+ * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
+ * EMAC count is possible. As it is needed for the Kilauea/Haleakala
+ * 405EX/405EXr eval board, using the same binary.
+ */
+#if defined(CONFIG_BOARD_EMAC_COUNT)
+#define LAST_EMAC_NUM	board_emac_count()
+#else /* CONFIG_BOARD_EMAC_COUNT */
+#if defined(CONFIG_HAS_ETH3)
+#define LAST_EMAC_NUM	4
+#elif defined(CONFIG_HAS_ETH2)
+#define LAST_EMAC_NUM	3
+#elif defined(CONFIG_HAS_ETH1)
+#define LAST_EMAC_NUM	2
+#else
+#define LAST_EMAC_NUM	1
+#endif
+#endif /* CONFIG_BOARD_EMAC_COUNT */
+
+/* normal boards start with EMAC0 */
+#if !defined(CONFIG_EMAC_NR_START)
+#define CONFIG_EMAC_NR_START	0
+#endif
+
+#define MAL_RX_DESC_SIZE	2048
+#define MAL_TX_DESC_SIZE	2048
+#define MAL_ALLOC_SIZE		(MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes and externals.
+ *-----------------------------------------------------------------------------*/
+static void enet_rcv (struct eth_device *dev, unsigned long malisr);
+
+int enetInt (struct eth_device *dev);
+static void mal_err (struct eth_device *dev, unsigned long isr,
+		     unsigned long uic, unsigned long maldef,
+		     unsigned long mal_errr);
+static void emac_err (struct eth_device *dev, unsigned long isr);
+
+extern int phy_setup_aneg (char *devname, unsigned char addr);
+extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short *value);
+extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value);
+
+int board_emac_count(void);
+
+static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
+{
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_405EX)
+	u32 val;
+
+	mfsdr(sdr_mfr, val);
+	val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
+	mtsdr(sdr_mfr, val);
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	u32 val;
+
+	mfsdr(SDR0_ETH_CFG, val);
+	val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
+	mtsdr(SDR0_ETH_CFG, val);
+#endif
+}
+
+static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
+{
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_405EX)
+	u32 val;
+
+	mfsdr(sdr_mfr, val);
+	val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
+	mtsdr(sdr_mfr, val);
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	u32 val;
+
+	mfsdr(SDR0_ETH_CFG, val);
+	val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
+	mtsdr(SDR0_ETH_CFG, val);
+#endif
+}
+
+/*-----------------------------------------------------------------------------+
+| ppc_4xx_eth_halt
+| Disable MAL channel, and EMACn
++-----------------------------------------------------------------------------*/
+static void ppc_4xx_eth_halt (struct eth_device *dev)
+{
+	EMAC_4XX_HW_PST hw_p = dev->priv;
+	u32 val = 10000;
+
+	out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000);	/* disable emac interrupts */
+
+	/* 1st reset MAL channel */
+	/* Note: writing a 0 to a channel has no effect */
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+	mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
+#else
+	mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
+#endif
+	mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
+
+	/* wait for reset */
+	while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
+		udelay (1000);	/* Delay 1 MS so as not to hammer the register */
+		val--;
+		if (val == 0)
+			break;
+	}
+
+	/* provide clocks for EMAC internal loopback  */
+	emac_loopback_enable(hw_p);
+
+	/* EMAC RESET */
+	out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+
+	/* remove clocks for EMAC internal loopback  */
+	emac_loopback_disable(hw_p);
+
+#ifndef CONFIG_NETCONSOLE
+	hw_p->print_speed = 1;	/* print speed message again next time */
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	/* don't bypass the TAHOE0/TAHOE1 cores for Linux */
+	mfsdr(SDR0_ETH_CFG, val);
+	val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+	mtsdr(SDR0_ETH_CFG, val);
+#endif
+
+	return;
+}
+
+#if defined (CONFIG_440GX)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
+{
+	unsigned long pfc1;
+	unsigned long zmiifer;
+	unsigned long rmiifer;
+
+	mfsdr(sdr_pfc1, pfc1);
+	pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
+
+	zmiifer = 0;
+	rmiifer = 0;
+
+	switch (pfc1) {
+	case 1:
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
+		break;
+	case 2:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
+		break;
+	case 3:
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 4:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
+		break;
+	case 5:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
+		break;
+	case 6:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		break;
+	case 0:
+	default:
+		zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
+		rmiifer = 0x0;
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
+		break;
+	}
+
+	/* Ensure we setup mdio for this devnum and ONLY this devnum */
+	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
+
+	out_be32((void *)ZMII_FER, zmiifer);
+	out_be32((void *)RGMII_FER, rmiifer);
+
+	return ((int)pfc1);
+}
+#endif	/* CONFIG_440_GX */
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
+{
+	unsigned long zmiifer=0x0;
+	unsigned long pfc1;
+
+	mfsdr(sdr_pfc1, pfc1);
+	pfc1 &= SDR0_PFC1_SELECT_MASK;
+
+	switch (pfc1) {
+	case SDR0_PFC1_SELECT_CONFIG_2:
+		/* 1 x GMII port */
+		out_be32((void *)ZMII_FER, 0x00);
+		out_be32((void *)RGMII_FER, 0x00000037);
+		bis->bi_phymode[0] = BI_PHYMODE_GMII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		break;
+	case SDR0_PFC1_SELECT_CONFIG_4:
+		/* 2 x RGMII ports */
+		out_be32((void *)ZMII_FER, 0x00);
+		out_be32((void *)RGMII_FER, 0x00000055);
+		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+		break;
+	case SDR0_PFC1_SELECT_CONFIG_6:
+		/* 2 x SMII ports */
+		out_be32((void *)ZMII_FER,
+			 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
+			 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
+		out_be32((void *)RGMII_FER, 0x00000000);
+		bis->bi_phymode[0] = BI_PHYMODE_SMII;
+		bis->bi_phymode[1] = BI_PHYMODE_SMII;
+		break;
+	case SDR0_PFC1_SELECT_CONFIG_1_2:
+		/* only 1 x MII supported */
+		out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
+		out_be32((void *)RGMII_FER, 0x00000000);
+		bis->bi_phymode[0] = BI_PHYMODE_MII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		break;
+	default:
+		break;
+	}
+
+	/* Ensure we setup mdio for this devnum and ONLY this devnum */
+	zmiifer = in_be32((void *)ZMII_FER);
+	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
+	out_be32((void *)ZMII_FER, zmiifer);
+
+	return ((int)0x0);
+}
+#endif	/* CONFIG_440EPX */
+
+#if defined(CONFIG_405EX)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
+{
+	u32 rgmiifer = 0;
+
+	/*
+	 * The 405EX(r)'s RGMII bridge can operate in one of several
+	 * modes, only one of which (2 x RGMII) allows the
+	 * simultaneous use of both EMACs on the 405EX.
+	 */
+
+	switch (CONFIG_EMAC_PHY_MODE) {
+
+	case EMAC_PHY_MODE_NONE:
+		/* No ports */
+		rgmiifer |= RGMII_FER_DIS	<< 0;
+		rgmiifer |= RGMII_FER_DIS	<< 4;
+		out_be32((void *)RGMII_FER, rgmiifer);
+		bis->bi_phymode[0] = BI_PHYMODE_NONE;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		break;
+	case EMAC_PHY_MODE_NONE_RGMII:
+		/* 1 x RGMII port on channel 0 */
+		rgmiifer |= RGMII_FER_RGMII	<< 0;
+		rgmiifer |= RGMII_FER_DIS	<< 4;
+		out_be32((void *)RGMII_FER, rgmiifer);
+		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		break;
+	case EMAC_PHY_MODE_RGMII_NONE:
+		/* 1 x RGMII port on channel 1 */
+		rgmiifer |= RGMII_FER_DIS	<< 0;
+		rgmiifer |= RGMII_FER_RGMII	<< 4;
+		out_be32((void *)RGMII_FER, rgmiifer);
+		bis->bi_phymode[0] = BI_PHYMODE_NONE;
+		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+		break;
+	case EMAC_PHY_MODE_RGMII_RGMII:
+		/* 2 x RGMII ports */
+		rgmiifer |= RGMII_FER_RGMII	<< 0;
+		rgmiifer |= RGMII_FER_RGMII	<< 4;
+		out_be32((void *)RGMII_FER, rgmiifer);
+		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+		break;
+	case EMAC_PHY_MODE_NONE_GMII:
+		/* 1 x GMII port on channel 0 */
+		rgmiifer |= RGMII_FER_GMII	<< 0;
+		rgmiifer |= RGMII_FER_DIS	<< 4;
+		out_be32((void *)RGMII_FER, rgmiifer);
+		bis->bi_phymode[0] = BI_PHYMODE_GMII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		break;
+	case EMAC_PHY_MODE_NONE_MII:
+		/* 1 x MII port on channel 0 */
+		rgmiifer |= RGMII_FER_MII	<< 0;
+		rgmiifer |= RGMII_FER_DIS	<< 4;
+		out_be32((void *)RGMII_FER, rgmiifer);
+		bis->bi_phymode[0] = BI_PHYMODE_MII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		break;
+	case EMAC_PHY_MODE_GMII_NONE:
+		/* 1 x GMII port on channel 1 */
+		rgmiifer |= RGMII_FER_DIS	<< 0;
+		rgmiifer |= RGMII_FER_GMII	<< 4;
+		out_be32((void *)RGMII_FER, rgmiifer);
+		bis->bi_phymode[0] = BI_PHYMODE_NONE;
+		bis->bi_phymode[1] = BI_PHYMODE_GMII;
+		break;
+	case EMAC_PHY_MODE_MII_NONE:
+		/* 1 x MII port on channel 1 */
+		rgmiifer |= RGMII_FER_DIS	<< 0;
+		rgmiifer |= RGMII_FER_MII	<< 4;
+		out_be32((void *)RGMII_FER, rgmiifer);
+		bis->bi_phymode[0] = BI_PHYMODE_NONE;
+		bis->bi_phymode[1] = BI_PHYMODE_MII;
+		break;
+	default:
+		break;
+	}
+
+	/* Ensure we setup mdio for this devnum and ONLY this devnum */
+	rgmiifer = in_be32((void *)RGMII_FER);
+	rgmiifer |= (1 << (19-devnum));
+	out_be32((void *)RGMII_FER, rgmiifer);
+
+	return ((int)0x0);
+}
+#endif  /* CONFIG_405EX */
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
+{
+	u32 eth_cfg;
+	u32 zmiifer;		/* ZMII0_FER reg. */
+	u32 rmiifer;		/* RGMII0_FER reg. Bridge 0 */
+	u32 rmiifer1;		/* RGMII0_FER reg. Bridge 1 */
+	int mode;
+
+	zmiifer  = 0;
+	rmiifer  = 0;
+	rmiifer1 = 0;
+
+#if defined(CONFIG_460EX)
+	mode = 9;
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
+	    ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
+		mode = 11; /* config SGMII */
+#else
+	mode = 10;
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
+	    ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
+	    ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
+		mode = 12; /* config SGMII */
+#endif
+
+	/* TODO:
+	 * NOTE: 460GT has 2 RGMII bridge cores:
+	 *		emac0 ------ RGMII0_BASE
+	 *		           |
+	 *		emac1 -----+
+	 *
+	 *		emac2 ------ RGMII1_BASE
+	 *		           |
+	 *		emac3 -----+
+	 *
+	 *	460EX has 1 RGMII bridge core:
+	 *	and RGMII1_BASE is disabled
+	 *		emac0 ------ RGMII0_BASE
+	 *		           |
+	 *		emac1 -----+
+	 */
+
+	/*
+	 * Right now only 2*RGMII is supported. Please extend when needed.
+	 * sr - 2008-02-19
+	 * Add SGMII support.
+	 * vg - 2008-07-28
+	 */
+	switch (mode) {
+	case 1:
+		/* 1 MII - 460EX */
+		/* GMC0 EMAC4_0, ZMII Bridge */
+		zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
+		bis->bi_phymode[0] = BI_PHYMODE_MII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		bis->bi_phymode[2] = BI_PHYMODE_NONE;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 2:
+		/* 2 MII - 460GT */
+		/* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
+		zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
+		bis->bi_phymode[0] = BI_PHYMODE_MII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		bis->bi_phymode[2] = BI_PHYMODE_MII;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 3:
+		/* 2 RMII - 460EX */
+		/* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
+		bis->bi_phymode[0] = BI_PHYMODE_RMII;
+		bis->bi_phymode[1] = BI_PHYMODE_RMII;
+		bis->bi_phymode[2] = BI_PHYMODE_NONE;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 4:
+		/* 4 RMII - 460GT */
+		/* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
+		/* ZMII Bridge */
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_RMII;
+		bis->bi_phymode[1] = BI_PHYMODE_RMII;
+		bis->bi_phymode[2] = BI_PHYMODE_RMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RMII;
+		break;
+	case 5:
+		/* 2 SMII - 460EX */
+		/* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
+		bis->bi_phymode[0] = BI_PHYMODE_SMII;
+		bis->bi_phymode[1] = BI_PHYMODE_SMII;
+		bis->bi_phymode[2] = BI_PHYMODE_NONE;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 6:
+		/* 4 SMII - 460GT */
+		/* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
+		/* ZMII Bridge */
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_SMII;
+		bis->bi_phymode[1] = BI_PHYMODE_SMII;
+		bis->bi_phymode[2] = BI_PHYMODE_SMII;
+		bis->bi_phymode[3] = BI_PHYMODE_SMII;
+		break;
+	case 7:
+		/* This is the default mode that we want for board bringup - Maple */
+		/* 1 GMII - 460EX */
+		/* GMC0 EMAC4_0, RGMII Bridge 0 */
+		rmiifer |= RGMII_FER_MDIO(0);
+
+		if (devnum == 0) {
+			rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
+			bis->bi_phymode[0] = BI_PHYMODE_GMII;
+			bis->bi_phymode[1] = BI_PHYMODE_NONE;
+			bis->bi_phymode[2] = BI_PHYMODE_NONE;
+			bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		} else {
+			rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
+			bis->bi_phymode[0] = BI_PHYMODE_NONE;
+			bis->bi_phymode[1] = BI_PHYMODE_GMII;
+			bis->bi_phymode[2] = BI_PHYMODE_NONE;
+			bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		}
+		break;
+	case 8:
+		/* 2 GMII - 460GT */
+		/* GMC0 EMAC4_0, RGMII Bridge 0 */
+		/* GMC1 EMAC4_2, RGMII Bridge 1 */
+		rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2);	/* CH0CFG - EMAC0 */
+		rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2);	/* CH0CFG - EMAC2 */
+		rmiifer |= RGMII_FER_MDIO(0);			/* enable MDIO - EMAC0 */
+		rmiifer1 |= RGMII_FER_MDIO(0);			/* enable MDIO - EMAC2 */
+
+		bis->bi_phymode[0] = BI_PHYMODE_GMII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		bis->bi_phymode[2] = BI_PHYMODE_GMII;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 9:
+		/* 2 RGMII - 460EX */
+		/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
+		rmiifer |= RGMII_FER_MDIO(0);			/* enable MDIO - EMAC0 */
+
+		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[2] = BI_PHYMODE_NONE;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 10:
+		/* 4 RGMII - 460GT */
+		/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+		/* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
+		rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
+		rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
+		break;
+	case 11:
+		/* 2 SGMII - 460EX */
+		bis->bi_phymode[0] = BI_PHYMODE_SGMII;
+		bis->bi_phymode[1] = BI_PHYMODE_SGMII;
+		bis->bi_phymode[2] = BI_PHYMODE_NONE;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 12:
+		/* 3 SGMII - 460GT */
+		bis->bi_phymode[0] = BI_PHYMODE_SGMII;
+		bis->bi_phymode[1] = BI_PHYMODE_SGMII;
+		bis->bi_phymode[2] = BI_PHYMODE_SGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	default:
+		break;
+	}
+
+	/* Set EMAC for MDIO */
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	out_be32((void *)RGMII_FER, rmiifer);
+#if defined(CONFIG_460GT)
+	out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
+#endif
+
+	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	return 0;
+}
+#endif /* CONFIG_460EX || CONFIG_460GT */
+
+static inline void *malloc_aligned(u32 size, u32 align)
+{
+	return (void *)(((u32)malloc(size + align) + align - 1) &
+			~(align - 1));
+}
+
+static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
+{
+	int i;
+	unsigned long reg = 0;
+	unsigned long msr;
+	unsigned long speed;
+	unsigned long duplex;
+	unsigned long failsafe;
+	unsigned mode_reg;
+	unsigned short devnum;
+	unsigned short reg_short;
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+	sys_info_t sysinfo;
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+	int ethgroup = -1;
+#endif
+#endif
+	u32 bd_cached;
+	u32 bd_uncached = 0;
+#ifdef CONFIG_4xx_DCACHE
+	static u32 last_used_ea = 0;
+#endif
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+	int rgmii_channel;
+#endif
+
+	EMAC_4XX_HW_PST hw_p = dev->priv;
+
+	/* before doing anything, figure out if we have a MAC address */
+	/* if not, bail */
+	if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
+		printf("ERROR: ethaddr not set!\n");
+		return -1;
+	}
+
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+	/* Need to get the OPB frequency so we can access the PHY */
+	get_sys_info (&sysinfo);
+#endif
+
+	msr = mfmsr ();
+	mtmsr (msr & ~(MSR_EE));	/* disable interrupts */
+
+	devnum = hw_p->devnum;
+
+#ifdef INFO_4XX_ENET
+	/* AS.HARNOIS
+	 * We should have :
+	 * hw_p->stats.pkts_handled <=	hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
+	 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
+	 * is possible that new packets (without relationship with
+	 * current transfer) have got the time to arrived before
+	 * netloop calls eth_halt
+	 */
+	printf ("About preceeding transfer (eth%d):\n"
+		"- Sent packet number %d\n"
+		"- Received packet number %d\n"
+		"- Handled packet number %d\n",
+		hw_p->devnum,
+		hw_p->stats.pkts_tx,
+		hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
+
+	hw_p->stats.pkts_tx = 0;
+	hw_p->stats.pkts_rx = 0;
+	hw_p->stats.pkts_handled = 0;
+	hw_p->print_speed = 1;	/* print speed message again next time */
+#endif
+
+	hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
+	hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
+
+	hw_p->rx_slot = 0;	/* MAL Receive Slot */
+	hw_p->rx_i_index = 0;	/* Receive Interrupt Queue Index */
+	hw_p->rx_u_index = 0;	/* Receive User Queue Index */
+
+	hw_p->tx_slot = 0;	/* MAL Transmit Slot */
+	hw_p->tx_i_index = 0;	/* Transmit Interrupt Queue Index */
+	hw_p->tx_u_index = 0;	/* Transmit User Queue Index */
+
+#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+	/* set RMII mode */
+	/* NOTE: 440GX spec states that mode is mutually exclusive */
+	/* NOTE: Therefore, disable all other EMACS, since we handle */
+	/* NOTE: only one emac at a time */
+	reg = 0;
+	out_be32((void *)ZMII_FER, 0);
+	udelay (100);
+
+#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+	out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
+#elif defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
+#endif
+
+	out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
+#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
+#if defined(CONFIG_405EX)
+	ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
+#endif
+
+	sync();
+
+	/* provide clocks for EMAC internal loopback  */
+	emac_loopback_enable(hw_p);
+
+	/* EMAC RESET */
+	out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+
+	/* remove clocks for EMAC internal loopback  */
+	emac_loopback_disable(hw_p);
+
+	failsafe = 1000;
+	while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
+		udelay (1000);
+		failsafe--;
+	}
+	if (failsafe <= 0)
+		printf("\nProblem resetting EMAC!\n");
+
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+	/* Whack the M1 register */
+	mode_reg = 0x0;
+	mode_reg &= ~0x00000038;
+	if (sysinfo.freqOPB <= 50000000);
+	else if (sysinfo.freqOPB <= 66666667)
+		mode_reg |= EMAC_M1_OBCI_66;
+	else if (sysinfo.freqOPB <= 83333333)
+		mode_reg |= EMAC_M1_OBCI_83;
+	else if (sysinfo.freqOPB <= 100000000)
+		mode_reg |= EMAC_M1_OBCI_100;
+	else
+		mode_reg |= EMAC_M1_OBCI_GT100;
+
+	out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
+#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
+
+#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
+    defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
+	if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
+		/*
+		 * In SGMII mode, GPCS access is needed for
+		 * communication with the internal SGMII SerDes.
+		 */
+		switch (devnum) {
+#if defined(CONFIG_GPCS_PHY_ADDR)
+		case 0:
+			reg = CONFIG_GPCS_PHY_ADDR;
+			break;
+#endif
+#if defined(CONFIG_GPCS_PHY1_ADDR)
+		case 1:
+			reg = CONFIG_GPCS_PHY1_ADDR;
+			break;
+#endif
+#if defined(CONFIG_GPCS_PHY2_ADDR)
+		case 2:
+			reg = CONFIG_GPCS_PHY2_ADDR;
+			break;
+#endif
+#if defined(CONFIG_GPCS_PHY3_ADDR)
+		case 3:
+			reg = CONFIG_GPCS_PHY3_ADDR;
+			break;
+#endif
+		}
+
+		mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
+		mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg);
+		out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
+
+		/* Configure GPCS interface to recommended setting for SGMII */
+		miiphy_reset(dev->name, reg);
+		miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
+		miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
+		miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX     */
+	}
+#endif /* defined(CONFIG_GPCS_PHY_ADDR) */
+
+	/* wait for PHY to complete auto negotiation */
+	reg_short = 0;
+	switch (devnum) {
+	case 0:
+		reg = CONFIG_PHY_ADDR;
+		break;
+#if defined (CONFIG_PHY1_ADDR)
+	case 1:
+		reg = CONFIG_PHY1_ADDR;
+		break;
+#endif
+#if defined (CONFIG_PHY2_ADDR)
+	case 2:
+		reg = CONFIG_PHY2_ADDR;
+		break;
+#endif
+#if defined (CONFIG_PHY3_ADDR)
+	case 3:
+		reg = CONFIG_PHY3_ADDR;
+		break;
+#endif
+	default:
+		reg = CONFIG_PHY_ADDR;
+		break;
+	}
+
+	bis->bi_phynum[devnum] = reg;
+
+	if (reg == CONFIG_FIXED_PHY)
+		goto get_speed;
+
+#if defined(CONFIG_PHY_RESET)
+	/*
+	 * Reset the phy, only if its the first time through
+	 * otherwise, just check the speeds & feeds
+	 */
+	if (hw_p->first_init == 0) {
+#if defined(CONFIG_M88E1111_PHY)
+		miiphy_write (dev->name, reg, 0x14, 0x0ce3);
+		miiphy_write (dev->name, reg, 0x18, 0x4101);
+		miiphy_write (dev->name, reg, 0x09, 0x0e00);
+		miiphy_write (dev->name, reg, 0x04, 0x01e1);
+#endif
+#if defined(CONFIG_M88E1112_PHY)
+		if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
+			/*
+			 * Marvell 88E1112 PHY needs to have the SGMII MAC
+			 * interace (page 2) properly configured to
+			 * communicate with the 460EX/GT GPCS interface.
+			 */
+
+			/* Set access to Page 2 */
+			miiphy_write(dev->name, reg, 0x16, 0x0002);
+
+			miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
+			miiphy_read(dev->name, reg, 0x1a, &reg_short);
+			reg_short |= 0x8000; /* bypass Auto-Negotiation */
+			miiphy_write(dev->name, reg, 0x1a, reg_short);
+			miiphy_reset(dev->name, reg); /* reset MAC interface */
+
+			/* Reset access to Page 0 */
+			miiphy_write(dev->name, reg, 0x16, 0x0000);
+		}
+#endif /* defined(CONFIG_M88E1112_PHY) */
+		miiphy_reset (dev->name, reg);
+
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+
+#if defined(CONFIG_CIS8201_PHY)
+		/*
+		 * Cicada 8201 PHY needs to have an extended register whacked
+		 * for RGMII mode.
+		 */
+		if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
+#if defined(CONFIG_CIS8201_SHORT_ETCH)
+			miiphy_write (dev->name, reg, 23, 0x1300);
+#else
+			miiphy_write (dev->name, reg, 23, 0x1000);
+#endif
+			/*
+			 * Vitesse VSC8201/Cicada CIS8201 errata:
+			 * Interoperability problem with Intel 82547EI phys
+			 * This work around (provided by Vitesse) changes
+			 * the default timer convergence from 8ms to 12ms
+			 */
+			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+			miiphy_write (dev->name, reg, 0x08, 0x0200);
+			miiphy_write (dev->name, reg, 0x1f, 0x52b5);
+			miiphy_write (dev->name, reg, 0x02, 0x0004);
+			miiphy_write (dev->name, reg, 0x01, 0x0671);
+			miiphy_write (dev->name, reg, 0x00, 0x8fae);
+			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+			miiphy_write (dev->name, reg, 0x08, 0x0000);
+			miiphy_write (dev->name, reg, 0x1f, 0x0000);
+			/* end Vitesse/Cicada errata */
+		}
+#endif /* defined(CONFIG_CIS8201_PHY) */
+
+#if defined(CONFIG_ET1011C_PHY)
+		/*
+		 * Agere ET1011c PHY needs to have an extended register whacked
+		 * for RGMII mode.
+		 */
+		if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
+			miiphy_read (dev->name, reg, 0x16, &reg_short);
+			reg_short &= ~(0x7);
+			reg_short |= 0x6;	/* RGMII DLL Delay*/
+			miiphy_write (dev->name, reg, 0x16, reg_short);
+
+			miiphy_read (dev->name, reg, 0x17, &reg_short);
+			reg_short &= ~(0x40);
+			miiphy_write (dev->name, reg, 0x17, reg_short);
+
+			miiphy_write(dev->name, reg, 0x1c, 0x74f0);
+		}
+#endif /* defined(CONFIG_ET1011C_PHY) */
+
+#endif /* defined(CONFIG_440GX) ... */
+		/* Start/Restart autonegotiation */
+		phy_setup_aneg (dev->name, reg);
+		udelay (1000);
+	}
+#endif /* defined(CONFIG_PHY_RESET) */
+
+	miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
+
+	/*
+	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
+	 */
+	if ((reg_short & PHY_BMSR_AUTN_ABLE)
+	    && !(reg_short & PHY_BMSR_AUTN_COMP)) {
+		puts ("Waiting for PHY auto negotiation to complete");
+		i = 0;
+		while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
+			/*
+			 * Timeout reached ?
+			 */
+			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+				puts (" TIMEOUT !\n");
+				break;
+			}
+
+			if ((i++ % 1000) == 0) {
+				putc ('.');
+			}
+			udelay (1000);	/* 1 ms */
+			miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
+		}
+		puts (" done\n");
+		udelay (500000);	/* another 500 ms (results in faster booting) */
+	}
+
+get_speed:
+	if (reg == CONFIG_FIXED_PHY) {
+		for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
+			if (devnum == fixed_phy_port[i].devnum) {
+				speed = fixed_phy_port[i].speed;
+				duplex = fixed_phy_port[i].duplex;
+				break;
+			}
+		}
+
+		if (i == ARRAY_SIZE(fixed_phy_port)) {
+			printf("ERROR: PHY (%s) not configured correctly!\n",
+				dev->name);
+			return -1;
+		}
+	} else {
+		speed = miiphy_speed(dev->name, reg);
+		duplex = miiphy_duplex(dev->name, reg);
+	}
+
+	if (hw_p->print_speed) {
+		hw_p->print_speed = 0;
+		printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
+			(int) speed, (duplex == HALF) ? "HALF" : "FULL",
+			hw_p->devnum);
+	}
+
+#if defined(CONFIG_440) && \
+    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
+    !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+	mfsdr(sdr_mfr, reg);
+	if (speed == 100) {
+		reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
+	} else {
+		reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
+	}
+	mtsdr(sdr_mfr, reg);
+#endif
+
+	/* Set ZMII/RGMII speed according to the phy link speed */
+	reg = in_be32((void *)ZMII_SSR);
+	if ( (speed == 100) || (speed == 1000) )
+		out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
+	else
+		out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
+
+	if ((devnum == 2) || (devnum == 3)) {
+		if (speed == 1000)
+			reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+		else if (speed == 100)
+			reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+		else if (speed == 10)
+			reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+		else {
+			printf("Error in RGMII Speed\n");
+			return -1;
+		}
+		out_be32((void *)RGMII_SSR, reg);
+	}
+#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+	if (devnum >= 2)
+		rgmii_channel = devnum - 2;
+	else
+		rgmii_channel = devnum;
+
+	if (speed == 1000)
+		reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
+	else if (speed == 100)
+		reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
+	else if (speed == 10)
+		reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
+	else {
+		printf("Error in RGMII Speed\n");
+		return -1;
+	}
+	out_be32((void *)RGMII_SSR, reg);
+#if defined(CONFIG_460GT)
+	if ((devnum == 2) || (devnum == 3))
+		out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
+#endif
+#endif
+
+	/* set the Mal configuration reg */
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
+	       MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
+#else
+	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
+	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
+	if (get_pvr() == PVR_440GP_RB) {
+		mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
+	}
+#endif
+
+	/*
+	 * Malloc MAL buffer desciptors, make sure they are
+	 * aligned on cache line boundary size
+	 * (401/403/IOP480 = 16, 405 = 32)
+	 * and doesn't cross cache block boundaries.
+	 */
+	if (hw_p->first_init == 0) {
+		debug("*** Allocating descriptor memory ***\n");
+
+		bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
+		if (!bd_cached) {
+			printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
+			return -1;
+		}
+
+#ifdef CONFIG_4xx_DCACHE
+		flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
+		if (!last_used_ea)
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+			bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
+#else
+			bd_uncached = bis->bi_memsize;
+#endif
+		else
+			bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
+
+		last_used_ea = bd_uncached;
+		program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
+			    TLB_WORD2_I_ENABLE);
+#else
+		bd_uncached = bd_cached;
+#endif
+		hw_p->tx_phys = bd_cached;
+		hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
+		hw_p->tx = (mal_desc_t *)(bd_uncached);
+		hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
+		debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
+	}
+
+	for (i = 0; i < NUM_TX_BUFF; i++) {
+		hw_p->tx[i].ctrl = 0;
+		hw_p->tx[i].data_len = 0;
+		if (hw_p->first_init == 0)
+			hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
+							 L1_CACHE_BYTES);
+		hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
+		if ((NUM_TX_BUFF - 1) == i)
+			hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
+		hw_p->tx_run[i] = -1;
+		debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
+	}
+
+	for (i = 0; i < NUM_RX_BUFF; i++) {
+		hw_p->rx[i].ctrl = 0;
+		hw_p->rx[i].data_len = 0;
+		hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
+		if ((NUM_RX_BUFF - 1) == i)
+			hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
+		hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
+		hw_p->rx_ready[i] = -1;
+		debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
+	}
+
+	reg = 0x00000000;
+
+	reg |= dev->enetaddr[0];	/* set high address */
+	reg = reg << 8;
+	reg |= dev->enetaddr[1];
+
+	out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
+
+	reg = 0x00000000;
+	reg |= dev->enetaddr[2];	/* set low address  */
+	reg = reg << 8;
+	reg |= dev->enetaddr[3];
+	reg = reg << 8;
+	reg |= dev->enetaddr[4];
+	reg = reg << 8;
+	reg |= dev->enetaddr[5];
+
+	out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
+
+	switch (devnum) {
+	case 1:
+		/* setup MAL tx & rx channel pointers */
+#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
+		mtdcr (maltxctp2r, hw_p->tx_phys);
+#else
+		mtdcr (maltxctp1r, hw_p->tx_phys);
+#endif
+#if defined(CONFIG_440)
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+		mtdcr (malrxctp8r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
+#else
+		mtdcr (malrxctp1r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
+#endif
+		break;
+#if defined (CONFIG_440GX)
+	case 2:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (maltxctp2r, hw_p->tx_phys);
+		mtdcr (malrxctp2r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+	case 3:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (maltxctp3r, hw_p->tx_phys);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (malrxctp3r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+#endif /* CONFIG_440GX */
+#if defined (CONFIG_460GT)
+	case 2:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (maltxctp2r, hw_p->tx_phys);
+		mtdcr (malrxctp16r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+	case 3:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (maltxctp3r, hw_p->tx_phys);
+		mtdcr (malrxctp24r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+#endif /* CONFIG_460GT */
+	case 0:
+	default:
+		/* setup MAL tx & rx channel pointers */
+#if defined(CONFIG_440)
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+#endif
+		mtdcr (maltxctp0r, hw_p->tx_phys);
+		mtdcr (malrxctp0r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+	}
+
+	/* Enable MAL transmit and receive channels */
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+	mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
+#else
+	mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
+#endif
+	mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
+
+	/* set transmit enable & receive enable */
+	out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+
+	mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
+
+	/* set rx-/tx-fifo size */
+	mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
+
+	/* set speed */
+	if (speed == _1000BASET) {
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+		unsigned long pfc1;
+
+		mfsdr (sdr_pfc1, pfc1);
+		pfc1 |= SDR0_PFC1_EM_1000;
+		mtsdr (sdr_pfc1, pfc1);
+#endif
+		mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
+	} else if (speed == _100BASET)
+		mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
+	else
+		mode_reg = mode_reg & ~0x00C00000;	/* 10 MBPS */
+	if (duplex == FULL)
+		mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
+
+	out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
+
+	/* Enable broadcast and indvidual address */
+	/* TBS: enabling runts as some misbehaved nics will send runts */
+	out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
+
+	/* we probably need to set the tx mode1 reg? maybe at tx time */
+
+	/* set transmit request threshold register */
+	out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000);	/* 256 byte threshold */
+
+	/* set receive	low/high water mark register */
+#if defined(CONFIG_440)
+	/* 440s has a 64 byte burst length */
+	out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
+#else
+	/* 405s have a 16 byte burst length */
+	out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
+#endif /* defined(CONFIG_440) */
+	out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
+
+	/* Set fifo limit entry in tx mode 0 */
+	out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
+	/* Frame gap set */
+	out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
+
+	/* Set EMAC IER */
+	hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
+	if (speed == _100BASET)
+		hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
+
+	out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff);	/* clear pending interrupts */
+	out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
+
+	if (hw_p->first_init == 0) {
+		/*
+		 * Connect interrupt service routines
+		 */
+		irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
+				    (interrupt_handler_t *) enetInt, dev);
+	}
+
+	mtmsr (msr);		/* enable interrupts again */
+
+	hw_p->bis = bis;
+	hw_p->first_init = 1;
+
+	return 0;
+}
+
+
+static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
+			      int len)
+{
+	struct enet_frame *ef_ptr;
+	ulong time_start, time_now;
+	unsigned long temp_txm0;
+	EMAC_4XX_HW_PST hw_p = dev->priv;
+
+	ef_ptr = (struct enet_frame *) ptr;
+
+	/*-----------------------------------------------------------------------+
+	 *  Copy in our address into the frame.
+	 *-----------------------------------------------------------------------*/
+	(void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
+
+	/*-----------------------------------------------------------------------+
+	 * If frame is too long or too short, modify length.
+	 *-----------------------------------------------------------------------*/
+	/* TBS: where does the fragment go???? */
+	if (len > ENET_MAX_MTU)
+		len = ENET_MAX_MTU;
+
+	/*   memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
+	memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
+	flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
+
+	/*-----------------------------------------------------------------------+
+	 * set TX Buffer busy, and send it
+	 *-----------------------------------------------------------------------*/
+	hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
+					EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
+		~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
+	if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
+		hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
+
+	hw_p->tx[hw_p->tx_slot].data_len = (short) len;
+	hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
+
+	sync();
+
+	out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
+		 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
+#ifdef INFO_4XX_ENET
+	hw_p->stats.pkts_tx++;
+#endif
+
+	/*-----------------------------------------------------------------------+
+	 * poll unitl the packet is sent and then make sure it is OK
+	 *-----------------------------------------------------------------------*/
+	time_start = get_timer (0);
+	while (1) {
+		temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
+		/* loop until either TINT turns on or 3 seconds elapse */
+		if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
+			/* transmit is done, so now check for errors
+			 * If there is an error, an interrupt should
+			 * happen when we return
+			 */
+			time_now = get_timer (0);
+			if ((time_now - time_start) > 3000) {
+				return (-1);
+			}
+		} else {
+			return (len);
+		}
+	}
+}
+
+int enetInt (struct eth_device *dev)
+{
+	int serviced;
+	int rc = -1;		/* default to not us */
+	u32 mal_isr;
+	u32 emac_isr = 0;
+	u32 mal_eob;
+	u32 uic_mal;
+	u32 uic_mal_err;
+	u32 uic_emac;
+	u32 uic_emac_b;
+	EMAC_4XX_HW_PST hw_p;
+
+	/*
+	 * Because the mal is generic, we need to get the current
+	 * eth device
+	 */
+#if defined(CONFIG_NET_MULTI)
+	dev = eth_get_dev();
+#else
+	dev = emac0_dev;
+#endif
+
+	hw_p = dev->priv;
+
+	/* enter loop that stays in interrupt code until nothing to service */
+	do {
+		serviced = 0;
+
+		uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
+		uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
+		uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
+		uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
+
+		if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
+		    && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
+		    && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
+			/* not for us */
+			return (rc);
+		}
+
+		/* get and clear controller status interrupts */
+		/* look at MAL and EMAC error interrupts */
+		if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
+			/* we have a MAL error interrupt */
+			mal_isr = mfdcr(malesr);
+			mal_err(dev, mal_isr, uic_mal_err,
+				 MAL_UIC_DEF, MAL_UIC_ERR);
+
+			/* clear MAL error interrupt status bits */
+			mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
+			      UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
+
+			return -1;
+		}
+
+		/* look for EMAC errors */
+		if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
+			emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
+			emac_err(dev, emac_isr);
+
+			/* clear EMAC error interrupt status bits */
+			mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
+			mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
+
+			return -1;
+		}
+
+		/* handle MAX TX EOB interrupt from a tx */
+		if (uic_mal & UIC_MAL_TXEOB) {
+			/* clear MAL interrupt status bits */
+			mal_eob = mfdcr(maltxeobisr);
+			mtdcr(maltxeobisr, mal_eob);
+			mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
+
+			/* indicate that we serviced an interrupt */
+			serviced = 1;
+			rc = 0;
+		}
+
+		/* handle MAL RX EOB interupt from a receive */
+		/* check for EOB on valid channels	     */
+		if (uic_mal & UIC_MAL_RXEOB) {
+			mal_eob = mfdcr(malrxeobisr);
+			if (mal_eob &
+			    (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
+				/* push packet to upper layer */
+				enet_rcv(dev, emac_isr);
+
+				/* clear MAL interrupt status bits */
+				mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
+
+				/* indicate that we serviced an interrupt */
+				serviced = 1;
+				rc = 0;
+			}
+		}
+	} while (serviced);
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------------+
+ *  MAL Error Routine
+ *-----------------------------------------------------------------------------*/
+static void mal_err (struct eth_device *dev, unsigned long isr,
+		     unsigned long uic, unsigned long maldef,
+		     unsigned long mal_errr)
+{
+	EMAC_4XX_HW_PST hw_p = dev->priv;
+
+	mtdcr (malesr, isr);	/* clear interrupt */
+
+	/* clear DE interrupt */
+	mtdcr (maltxdeir, 0xC0000000);
+	mtdcr (malrxdeir, 0x80000000);
+
+#ifdef INFO_4XX_ENET
+	printf ("\nMAL error occured.... ISR = %lx UIC = = %lx	MAL_DEF = %lx  MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
+#endif
+
+	eth_init (hw_p->bis);	/* start again... */
+}
+
+/*-----------------------------------------------------------------------------+
+ *  EMAC Error Routine
+ *-----------------------------------------------------------------------------*/
+static void emac_err (struct eth_device *dev, unsigned long isr)
+{
+	EMAC_4XX_HW_PST hw_p = dev->priv;
+
+	printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
+	out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
+}
+
+/*-----------------------------------------------------------------------------+
+ *  enet_rcv() handles the ethernet receive data
+ *-----------------------------------------------------------------------------*/
+static void enet_rcv (struct eth_device *dev, unsigned long malisr)
+{
+	struct enet_frame *ef_ptr;
+	unsigned long data_len;
+	unsigned long rx_eob_isr;
+	EMAC_4XX_HW_PST hw_p = dev->priv;
+
+	int handled = 0;
+	int i;
+	int loop_count = 0;
+
+	rx_eob_isr = mfdcr (malrxeobisr);
+	if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
+		/* clear EOB */
+		mtdcr (malrxeobisr, rx_eob_isr);
+
+		/* EMAC RX done */
+		while (1) {	/* do all */
+			i = hw_p->rx_slot;
+
+			if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
+			    || (loop_count >= NUM_RX_BUFF))
+				break;
+
+			loop_count++;
+			handled++;
+			data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff;	/* Get len */
+			if (data_len) {
+				if (data_len > ENET_MAX_MTU)	/* Check len */
+					data_len = 0;
+				else {
+					if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) {	/* Check Errors */
+						data_len = 0;
+						hw_p->stats.rx_err_log[hw_p->
+								       rx_err_index]
+							= hw_p->rx[i].ctrl;
+						hw_p->rx_err_index++;
+						if (hw_p->rx_err_index ==
+						    MAX_ERR_LOG)
+							hw_p->rx_err_index =
+								0;
+					}	/* emac_erros */
+				}	/* data_len < max mtu */
+			}	/* if data_len */
+			if (!data_len) {	/* no data */
+				hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY;	/* Free Recv Buffer */
+
+				hw_p->stats.data_len_err++;	/* Error at Rx */
+			}
+
+			/* !data_len */
+			/* AS.HARNOIS */
+			/* Check if user has already eaten buffer */
+			/* if not => ERROR */
+			else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
+				if (hw_p->is_receiving)
+					printf ("ERROR : Receive buffers are full!\n");
+				break;
+			} else {
+				hw_p->stats.rx_frames++;
+				hw_p->stats.rx += data_len;
+				ef_ptr = (struct enet_frame *) hw_p->rx[i].
+					data_ptr;
+#ifdef INFO_4XX_ENET
+				hw_p->stats.pkts_rx++;
+#endif
+				/* AS.HARNOIS
+				 * use ring buffer
+				 */
+				hw_p->rx_ready[hw_p->rx_i_index] = i;
+				hw_p->rx_i_index++;
+				if (NUM_RX_BUFF == hw_p->rx_i_index)
+					hw_p->rx_i_index = 0;
+
+				hw_p->rx_slot++;
+				if (NUM_RX_BUFF == hw_p->rx_slot)
+					hw_p->rx_slot = 0;
+
+				/*  AS.HARNOIS
+				 * free receive buffer only when
+				 * buffer has been handled (eth_rx)
+				 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
+				 */
+			}	/* if data_len */
+		}		/* while */
+	}			/* if EMACK_RXCHL */
+}
+
+
+static int ppc_4xx_eth_rx (struct eth_device *dev)
+{
+	int length;
+	int user_index;
+	unsigned long msr;
+	EMAC_4XX_HW_PST hw_p = dev->priv;
+
+	hw_p->is_receiving = 1; /* tell driver */
+
+	for (;;) {
+		/* AS.HARNOIS
+		 * use ring buffer and
+		 * get index from rx buffer desciptor queue
+		 */
+		user_index = hw_p->rx_ready[hw_p->rx_u_index];
+		if (user_index == -1) {
+			length = -1;
+			break;	/* nothing received - leave for() loop */
+		}
+
+		msr = mfmsr ();
+		mtmsr (msr & ~(MSR_EE));
+
+		length = hw_p->rx[user_index].data_len & 0x0fff;
+
+		/* Pass the packet up to the protocol layers. */
+		/*	 NetReceive(NetRxPackets[rxIdx], length - 4); */
+		/*	 NetReceive(NetRxPackets[i], length); */
+		invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
+					(u32)hw_p->rx[user_index].data_ptr +
+					length - 4);
+		NetReceive (NetRxPackets[user_index], length - 4);
+		/* Free Recv Buffer */
+		hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
+		/* Free rx buffer descriptor queue */
+		hw_p->rx_ready[hw_p->rx_u_index] = -1;
+		hw_p->rx_u_index++;
+		if (NUM_RX_BUFF == hw_p->rx_u_index)
+			hw_p->rx_u_index = 0;
+
+#ifdef INFO_4XX_ENET
+		hw_p->stats.pkts_handled++;
+#endif
+
+		mtmsr (msr);	/* Enable IRQ's */
+	}
+
+	hw_p->is_receiving = 0; /* tell driver */
+
+	return length;
+}
+
+int ppc_4xx_eth_initialize (bd_t * bis)
+{
+	static int virgin = 0;
+	struct eth_device *dev;
+	int eth_num = 0;
+	EMAC_4XX_HW_PST hw = NULL;
+	u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
+	u32 hw_addr[4];
+	u32 mal_ier;
+
+#if defined(CONFIG_440GX)
+	unsigned long pfc1;
+
+	mfsdr (sdr_pfc1, pfc1);
+	pfc1 &= ~(0x01e00000);
+	pfc1 |= 0x01200000;
+	mtsdr (sdr_pfc1, pfc1);
+#endif
+
+	/* first clear all mac-addresses */
+	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
+		memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
+
+	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
+		switch (eth_num) {
+		default:		/* fall through */
+		case 0:
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enetaddr, 6);
+			hw_addr[eth_num] = 0x0;
+			break;
+#ifdef CONFIG_HAS_ETH1
+		case 1:
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enet1addr, 6);
+			hw_addr[eth_num] = 0x100;
+			break;
+#endif
+#ifdef CONFIG_HAS_ETH2
+		case 2:
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enet2addr, 6);
+#if defined(CONFIG_460GT)
+			hw_addr[eth_num] = 0x300;
+#else
+			hw_addr[eth_num] = 0x400;
+#endif
+			break;
+#endif
+#ifdef CONFIG_HAS_ETH3
+		case 3:
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enet3addr, 6);
+#if defined(CONFIG_460GT)
+			hw_addr[eth_num] = 0x400;
+#else
+			hw_addr[eth_num] = 0x600;
+#endif
+			break;
+#endif
+		}
+	}
+
+	/* set phy num and mode */
+	bis->bi_phynum[0] = CONFIG_PHY_ADDR;
+	bis->bi_phymode[0] = 0;
+
+#if defined(CONFIG_PHY1_ADDR)
+	bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
+	bis->bi_phymode[1] = 0;
+#endif
+#if defined(CONFIG_440GX)
+	bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
+	bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
+	bis->bi_phymode[2] = 2;
+	bis->bi_phymode[3] = 2;
+#endif
+
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_405EX)
+	ppc_4xx_eth_setup_bridge(0, bis);
+#endif
+
+	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
+		/*
+		 * See if we can actually bring up the interface,
+		 * otherwise, skip it
+		 */
+		if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
+			bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
+			continue;
+		}
+
+		/* Allocate device structure */
+		dev = (struct eth_device *) malloc (sizeof (*dev));
+		if (dev == NULL) {
+			printf ("ppc_4xx_eth_initialize: "
+				"Cannot allocate eth_device %d\n", eth_num);
+			return (-1);
+		}
+		memset(dev, 0, sizeof(*dev));
+
+		/* Allocate our private use data */
+		hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
+		if (hw == NULL) {
+			printf ("ppc_4xx_eth_initialize: "
+				"Cannot allocate private hw data for eth_device %d",
+				eth_num);
+			free (dev);
+			return (-1);
+		}
+		memset(hw, 0, sizeof(*hw));
+
+		hw->hw_addr = hw_addr[eth_num];
+		memcpy (dev->enetaddr, ethaddr[eth_num], 6);
+		hw->devnum = eth_num;
+		hw->print_speed = 1;
+
+		sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
+		dev->priv = (void *) hw;
+		dev->init = ppc_4xx_eth_init;
+		dev->halt = ppc_4xx_eth_halt;
+		dev->send = ppc_4xx_eth_send;
+		dev->recv = ppc_4xx_eth_rx;
+
+		if (0 == virgin) {
+			/* set the MAL IER ??? names may change with new spec ??? */
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+			mal_ier =
+				MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
+				MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
+#else
+			mal_ier =
+				MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
+				MAL_IER_OPBE | MAL_IER_PLBE;
+#endif
+			mtdcr (malesr, 0xffffffff);	/* clear pending interrupts */
+			mtdcr (maltxdeir, 0xffffffff);	/* clear pending interrupts */
+			mtdcr (malrxdeir, 0xffffffff);	/* clear pending interrupts */
+			mtdcr (malier, mal_ier);
+
+			/* install MAL interrupt handler */
+			irq_install_handler (VECNUM_MAL_SERR,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_MAL_TXEOB,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_MAL_RXEOB,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_MAL_TXDE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_MAL_RXDE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			virgin = 1;
+		}
+
+#if defined(CONFIG_NET_MULTI)
+		eth_register (dev);
+#else
+		emac0_dev = dev;
+#endif
+
+#if defined(CONFIG_NET_MULTI)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+		miiphy_register (dev->name,
+				 emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
+#endif
+	}			/* end for each supported device */
+
+	return 0;
+}
+
+#if !defined(CONFIG_NET_MULTI)
+void eth_halt (void) {
+	if (emac0_dev) {
+		ppc_4xx_eth_halt(emac0_dev);
+		free(emac0_dev);
+		emac0_dev = NULL;
+	}
+}
+
+int eth_init (bd_t *bis)
+{
+	ppc_4xx_eth_initialize(bis);
+	if (emac0_dev) {
+		return ppc_4xx_eth_init(emac0_dev, bis);
+	} else {
+		printf("ERROR: ethaddr not set!\n");
+		return -1;
+	}
+}
+
+int eth_send(volatile void *packet, int length)
+{
+	return (ppc_4xx_eth_send(emac0_dev, packet, length));
+}
+
+int eth_rx(void)
+{
+	return (ppc_4xx_eth_rx(emac0_dev));
+}
+
+int emac4xx_miiphy_initialize (bd_t * bis)
+{
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+	miiphy_register ("ppc_4xx_eth0",
+			 emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
+
+	return 0;
+}
+#endif /* !defined(CONFIG_NET_MULTI) */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a084000..631336a 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	:= $(obj)libnet.a
 
 COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
+COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
 COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
 COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
 COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
@@ -34,20 +35,18 @@ COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
 COBJS-$(CONFIG_E1000) += e1000.o
 COBJS-$(CONFIG_EEPRO100) += eepro100.o
 COBJS-$(CONFIG_ENC28J60) += enc28j60.o
-COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o
+COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
 COBJS-$(CONFIG_GRETH) += greth.o
 COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
 COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
 COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o
 COBJS-$(CONFIG_MACB) += macb.o
-COBJS-$(CONFIG_MCFFEC) += mcffec.o
+COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
 COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
 COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
 COBJS-$(CONFIG_NATSEMI) += natsemi.o
-ifeq ($(CONFIG_DRIVER_NE2000),y)
-COBJS-y += ne2000.o
-COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o
-endif
+COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
+COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
 COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
 COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
 COBJS-$(CONFIG_DRIVER_NS7520_ETHERNET) += ns7520_eth.o
@@ -55,6 +54,7 @@ COBJS-$(CONFIG_NS8382X) += ns8382x.o
 COBJS-$(CONFIG_DRIVER_NS9750_ETHERNET) += ns9750_eth.o
 COBJS-$(CONFIG_PCNET) += pcnet.o
 COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
+COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
 COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o
 COBJS-$(CONFIG_RTL8139) += rtl8139.o
 COBJS-$(CONFIG_RTL8169) += rtl8169.o
diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c
new file mode 100644
index 0000000..d843397
--- /dev/null
+++ b/drivers/net/ax88180.c
@@ -0,0 +1,727 @@
+/*
+ * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
+ *
+ * This program is free software; you can distribute it and/or modify
+ * it under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ * This program is distributed in the hope it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
+ * USA.
+ */
+
+/*
+ * ========================================================================
+ * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
+ *
+ * The AX88180 Ethernet controller is a high performance and highly
+ * integrated local CPU bus Ethernet controller with embedded 40K bytes
+ * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
+ * embedded systems.
+ * The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet
+ * controller that supports both MII and RGMII interfaces and is
+ * compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards.
+ *
+ * Please visit ASIX's web site (http://www.asix.com.tw) for more
+ * details.
+ *
+ * Module Name	: ax88180.c
+ * Date		: 2008-07-07
+ * History
+ * 09/06/2006	: New release for AX88180 US2 chip.
+ * 07/07/2008	: Fix up the coding style and using inline functions
+ *		  instead of macros
+ * ========================================================================
+ */
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+#include "ax88180.h"
+
+/*
+ * ===========================================================================
+ * Local SubProgram Declaration
+ * ===========================================================================
+ */
+static void ax88180_rx_handler (struct eth_device *dev);
+static int ax88180_phy_initial (struct eth_device *dev);
+static void ax88180_meidia_config (struct eth_device *dev);
+static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev);
+static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev);
+static unsigned short ax88180_mdio_read (struct eth_device *dev,
+					 unsigned long regaddr);
+static void ax88180_mdio_write (struct eth_device *dev,
+				unsigned long regaddr, unsigned short regdata);
+
+/*
+ * ===========================================================================
+ * Local SubProgram Bodies
+ * ===========================================================================
+ */
+static int ax88180_mdio_check_complete (struct eth_device *dev)
+{
+	int us_cnt = 10000;
+	unsigned short tmpval;
+
+	/* MDIO read/write should not take more than 10 ms */
+	while (--us_cnt) {
+		tmpval = INW (dev, MDIOCTRL);
+		if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0))
+			break;
+	}
+
+	return us_cnt;
+}
+
+static unsigned short
+ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long tmpval = 0;
+
+	OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
+
+	if (ax88180_mdio_check_complete (dev))
+		tmpval = INW (dev, MDIODP);
+	else
+		printf ("Failed to read PHY register!\n");
+
+	return (unsigned short)(tmpval & 0xFFFF);
+}
+
+static void
+ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr,
+		    unsigned short regdata)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+
+	OUTW (dev, regdata, MDIODP);
+
+	OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
+
+	if (!ax88180_mdio_check_complete (dev))
+		printf ("Failed to write PHY register!\n");
+}
+
+static int ax88180_phy_reset (struct eth_device *dev)
+{
+	unsigned short delay_cnt = 500;
+
+	ax88180_mdio_write (dev, BMCR, (PHY_RESET | AUTONEG_EN));
+
+	/* Wait for the reset to complete, or time out (500 ms) */
+	while (ax88180_mdio_read (dev, BMCR) & PHY_RESET) {
+		udelay (1000);
+		if (--delay_cnt == 0) {
+			printf ("Failed to reset PHY!\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static void ax88180_mac_reset (struct eth_device *dev)
+{
+	unsigned long tmpval;
+	unsigned char i;
+
+	struct {
+		unsigned short offset, value;
+	} program_seq[] = {
+		{
+		MISC, MISC_NORMAL}, {
+		RXINDICATOR, DEFAULT_RXINDICATOR}, {
+		TXCMD, DEFAULT_TXCMD}, {
+		TXBS, DEFAULT_TXBS}, {
+		TXDES0, DEFAULT_TXDES0}, {
+		TXDES1, DEFAULT_TXDES1}, {
+		TXDES2, DEFAULT_TXDES2}, {
+		TXDES3, DEFAULT_TXDES3}, {
+		TXCFG, DEFAULT_TXCFG}, {
+		MACCFG2, DEFAULT_MACCFG2}, {
+		MACCFG3, DEFAULT_MACCFG3}, {
+		TXLEN, DEFAULT_TXLEN}, {
+		RXBTHD0, DEFAULT_RXBTHD0}, {
+		RXBTHD1, DEFAULT_RXBTHD1}, {
+		RXFULTHD, DEFAULT_RXFULTHD}, {
+		DOGTHD0, DEFAULT_DOGTHD0}, {
+	DOGTHD1, DEFAULT_DOGTHD1},};
+
+	OUTW (dev, MISC_RESET_MAC, MISC);
+	tmpval = INW (dev, MISC);
+
+	for (i = 0; i < (sizeof (program_seq) / sizeof (program_seq[0])); i++)
+		OUTW (dev, program_seq[i].value, program_seq[i].offset);
+}
+
+static int ax88180_poll_tx_complete (struct eth_device *dev)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long tmpval, txbs_txdp;
+	int TimeOutCnt = 10000;
+
+	txbs_txdp = 1 << priv->NextTxDesc;
+
+	while (TimeOutCnt--) {
+
+		tmpval = INW (dev, TXBS);
+
+		if ((tmpval & txbs_txdp) == 0)
+			break;
+
+		udelay (100);
+	}
+
+	if (TimeOutCnt)
+		return 0;
+	else
+		return -TimeOutCnt;
+}
+
+static void ax88180_rx_handler (struct eth_device *dev)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long data_size;
+	unsigned short rxcurt_ptr, rxbound_ptr, next_ptr;
+	int i;
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+	unsigned short *rxdata = (unsigned short *)NetRxPackets[0];
+#else
+	unsigned long *rxdata = (unsigned long *)NetRxPackets[0];
+#endif
+	unsigned short count;
+
+	rxcurt_ptr = INW (dev, RXCURT);
+	rxbound_ptr = INW (dev, RXBOUND);
+	next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
+
+	debug ("ax88180: RX original RXBOUND=0x%04x,"
+	       " RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
+
+	while (next_ptr != rxcurt_ptr) {
+
+		OUTW (dev, RX_START_READ, RXINDICATOR);
+
+		data_size = READ_RXBUF (dev) & 0xFFFF;
+
+		if ((data_size == 0) || (data_size > MAX_RX_SIZE)) {
+
+			OUTW (dev, RX_STOP_READ, RXINDICATOR);
+
+			ax88180_mac_reset (dev);
+			printf ("ax88180: Invalid Rx packet length!"
+				" (len=0x%04lx)\n", data_size);
+
+			debug ("ax88180: RX RXBOUND=0x%04x,"
+			       "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
+			return;
+		}
+
+		rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1;
+		rxbound_ptr &= RX_PAGE_NUM_MASK;
+
+		/* Comput access times */
+		count = (data_size + priv->PadSize) >> priv->BusWidth;
+
+		for (i = 0; i < count; i++) {
+			*(rxdata + i) = READ_RXBUF (dev);
+		}
+
+		OUTW (dev, RX_STOP_READ, RXINDICATOR);
+
+		/* Pass the packet up to the protocol layers. */
+		NetReceive (NetRxPackets[0], data_size);
+
+		OUTW (dev, rxbound_ptr, RXBOUND);
+
+		rxcurt_ptr = INW (dev, RXCURT);
+		rxbound_ptr = INW (dev, RXBOUND);
+		next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
+
+		debug ("ax88180: RX updated RXBOUND=0x%04x,"
+		       "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
+	}
+
+	return;
+}
+
+static int ax88180_phy_initial (struct eth_device *dev)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long tmp_regval;
+
+	/* Check avaliable PHY chipset  */
+	priv->PhyAddr = MARVELL_88E1111_PHYADDR;
+	priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
+
+	if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
+
+		debug ("ax88180: Found Marvell 88E1111 PHY."
+		       " (PHY Addr=0x%x)\n", priv->PhyAddr);
+
+		tmp_regval = ax88180_mdio_read (dev, M88_EXT_SSR);
+		if ((tmp_regval & HWCFG_MODE_MASK) == RGMII_COPPER_MODE) {
+
+			ax88180_mdio_write (dev, M88_EXT_SCR, DEFAULT_EXT_SCR);
+			if (ax88180_phy_reset (dev) < 0)
+				return 0;
+			ax88180_mdio_write (dev, M88_IER, LINK_CHANGE_INT);
+		}
+	} else {
+
+		priv->PhyAddr = CICADA_CIS8201_PHYADDR;
+		priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
+
+		if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
+
+			debug ("ax88180: Found CICADA CIS8201 PHY"
+			       " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
+			ax88180_mdio_write (dev, CIS_IMR,
+					    (CIS_INT_ENABLE | LINK_CHANGE_INT));
+
+			/* Set CIS_SMI_PRIORITY bit before force the media mode */
+			tmp_regval =
+			    ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
+			tmp_regval &= ~CIS_SMI_PRIORITY;
+			ax88180_mdio_write (dev, CIS_AUX_CTRL_STATUS,
+					    tmp_regval);
+		} else {
+			printf ("ax88180: Unknown PHY chipset!!\n");
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+static void ax88180_meidia_config (struct eth_device *dev)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long bmcr_val, bmsr_val;
+	unsigned long rxcfg_val, maccfg0_val, maccfg1_val;
+	unsigned long RealMediaMode;
+	int i;
+
+	/* Waiting 2 seconds for PHY link stable */
+	for (i = 0; i < 20000; i++) {
+		bmsr_val = ax88180_mdio_read (dev, BMSR);
+		if (bmsr_val & LINKOK) {
+			break;
+		}
+		udelay (100);
+	}
+
+	bmsr_val = ax88180_mdio_read (dev, BMSR);
+	debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
+
+	if (bmsr_val & LINKOK) {
+		bmcr_val = ax88180_mdio_read (dev, BMCR);
+
+		if (bmcr_val & AUTONEG_EN) {
+
+			/*
+			 * Waiting for Auto-negotiation completion, this may
+			 * take up to 5 seconds.
+			 */
+			debug ("ax88180: Auto-negotiation is "
+			       "enabled. Waiting for NWay completion..\n");
+			for (i = 0; i < 50000; i++) {
+				bmsr_val = ax88180_mdio_read (dev, BMSR);
+				if (bmsr_val & AUTONEG_COMPLETE) {
+					break;
+				}
+				udelay (100);
+			}
+		} else
+			debug ("ax88180: Auto-negotiation is disabled.\n");
+
+		debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n",
+		       (unsigned int)bmcr_val, (unsigned int)bmsr_val);
+
+		/* Get real media mode here */
+		if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
+			RealMediaMode = get_MarvellPHY_meida_mode (dev);
+		} else if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
+			RealMediaMode = get_CicadaPHY_meida_mode (dev);
+		} else {
+			RealMediaMode = MEDIA_1000FULL;
+		}
+
+		priv->LinkState = INS_LINK_UP;
+
+		switch (RealMediaMode) {
+		case MEDIA_1000FULL:
+			debug ("ax88180: 1000Mbps Full-duplex mode.\n");
+			rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
+			maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
+			maccfg1_val = GIGA_MODE_EN | RXFLOW_EN |
+			    FULLDUPLEX | DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_1000HALF:
+			debug ("ax88180: 1000Mbps Half-duplex mode.\n");
+			rxcfg_val = DEFAULT_RXCFG;
+			maccfg0_val = DEFAULT_MACCFG0;
+			maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_100FULL:
+			debug ("ax88180: 100Mbps Full-duplex mode.\n");
+			rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
+			maccfg0_val = SPEED100 | TXFLOW_ENABLE
+			    | DEFAULT_MACCFG0;
+			maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_100HALF:
+			debug ("ax88180: 100Mbps Half-duplex mode.\n");
+			rxcfg_val = DEFAULT_RXCFG;
+			maccfg0_val = SPEED100 | DEFAULT_MACCFG0;
+			maccfg1_val = DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_10FULL:
+			debug ("ax88180: 10Mbps Full-duplex mode.\n");
+			rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
+			maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
+			maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_10HALF:
+			debug ("ax88180: 10Mbps Half-duplex mode.\n");
+			rxcfg_val = DEFAULT_RXCFG;
+			maccfg0_val = DEFAULT_MACCFG0;
+			maccfg1_val = DEFAULT_MACCFG1;
+			break;
+		default:
+			debug ("ax88180: Unknow media mode.\n");
+			rxcfg_val = DEFAULT_RXCFG;
+			maccfg0_val = DEFAULT_MACCFG0;
+			maccfg1_val = DEFAULT_MACCFG1;
+
+			priv->LinkState = INS_LINK_DOWN;
+			break;
+		}
+
+	} else {
+		rxcfg_val = DEFAULT_RXCFG;
+		maccfg0_val = DEFAULT_MACCFG0;
+		maccfg1_val = DEFAULT_MACCFG1;
+
+		priv->LinkState = INS_LINK_DOWN;
+	}
+
+	OUTW (dev, rxcfg_val, RXCFG);
+	OUTW (dev, maccfg0_val, MACCFG0);
+	OUTW (dev, maccfg1_val, MACCFG1);
+
+	return;
+}
+
+static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev)
+{
+	unsigned long m88_ssr;
+	unsigned long MediaMode;
+
+	m88_ssr = ax88180_mdio_read (dev, M88_SSR);
+	switch (m88_ssr & SSR_MEDIA_MASK) {
+	case SSR_1000FULL:
+		MediaMode = MEDIA_1000FULL;
+		break;
+	case SSR_1000HALF:
+		MediaMode = MEDIA_1000HALF;
+		break;
+	case SSR_100FULL:
+		MediaMode = MEDIA_100FULL;
+		break;
+	case SSR_100HALF:
+		MediaMode = MEDIA_100HALF;
+		break;
+	case SSR_10FULL:
+		MediaMode = MEDIA_10FULL;
+		break;
+	case SSR_10HALF:
+		MediaMode = MEDIA_10HALF;
+		break;
+	default:
+		MediaMode = MEDIA_UNKNOWN;
+		break;
+	}
+
+	return MediaMode;
+}
+
+static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev)
+{
+	unsigned long tmp_regval;
+	unsigned long MediaMode;
+
+	tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
+	switch (tmp_regval & CIS_MEDIA_MASK) {
+	case CIS_1000FULL:
+		MediaMode = MEDIA_1000FULL;
+		break;
+	case CIS_1000HALF:
+		MediaMode = MEDIA_1000HALF;
+		break;
+	case CIS_100FULL:
+		MediaMode = MEDIA_100FULL;
+		break;
+	case CIS_100HALF:
+		MediaMode = MEDIA_100HALF;
+		break;
+	case CIS_10FULL:
+		MediaMode = MEDIA_10FULL;
+		break;
+	case CIS_10HALF:
+		MediaMode = MEDIA_10HALF;
+		break;
+	default:
+		MediaMode = MEDIA_UNKNOWN;
+		break;
+	}
+
+	return MediaMode;
+}
+
+static void ax88180_halt (struct eth_device *dev)
+{
+	/* Disable AX88180 TX/RX functions */
+	OUTW (dev, WAKEMOD, CMD);
+}
+
+static int ax88180_init (struct eth_device *dev, bd_t * bd)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned short tmp_regval;
+
+	ax88180_mac_reset (dev);
+
+	/* Disable interrupt */
+	OUTW (dev, CLEAR_IMR, IMR);
+
+	/* Disable AX88180 TX/RX functions */
+	OUTW (dev, WAKEMOD, CMD);
+
+	/* Fill the MAC address */
+	tmp_regval =
+	    dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8);
+	OUTW (dev, tmp_regval, MACID0);
+
+	tmp_regval =
+	    dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8);
+	OUTW (dev, tmp_regval, MACID1);
+
+	tmp_regval =
+	    dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
+	OUTW (dev, tmp_regval, MACID2);
+
+	ax88180_meidia_config (dev);
+
+	OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
+
+	/* Initial variables here */
+	priv->FirstTxDesc = TXDP0;
+	priv->NextTxDesc = TXDP0;
+
+	/* Check if there is any invalid interrupt status and clear it. */
+	OUTW (dev, INW (dev, ISR), ISR);
+
+	/* Start AX88180 TX/RX functions */
+	OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD);
+
+	return 0;
+}
+
+/* Get a data block via Ethernet */
+static int ax88180_recv (struct eth_device *dev)
+{
+	unsigned short ISR_Status;
+	unsigned short tmp_regval;
+
+	/* Read and check interrupt status here. */
+	ISR_Status = INW (dev, ISR);
+
+	while (ISR_Status) {
+		/* Clear the interrupt status */
+		OUTW (dev, ISR_Status, ISR);
+
+		debug ("\nax88180: The interrupt status = 0x%04x\n",
+		       ISR_Status);
+
+		if (ISR_Status & ISR_PHY) {
+			/* Read ISR register once to clear PHY interrupt bit */
+			tmp_regval = ax88180_mdio_read (dev, M88_ISR);
+			ax88180_meidia_config (dev);
+		}
+
+		if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
+			ax88180_rx_handler (dev);
+		}
+
+		/* Read and check interrupt status again */
+		ISR_Status = INW (dev, ISR);
+	}
+
+	return 0;
+}
+
+/* Send a data block via Ethernet. */
+static int
+ax88180_send (struct eth_device *dev, volatile void *packet, int length)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned short TXDES_addr;
+	unsigned short txcmd_txdp, txbs_txdp;
+	unsigned short tmp_data;
+	int i;
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+	volatile unsigned short *txdata = (volatile unsigned short *)packet;
+#else
+	volatile unsigned long *txdata = (volatile unsigned long *)packet;
+#endif
+	unsigned short count;
+
+	if (priv->LinkState != INS_LINK_UP) {
+		return 0;
+	}
+
+	priv->FirstTxDesc = priv->NextTxDesc;
+	txbs_txdp = 1 << priv->FirstTxDesc;
+
+	debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc);
+
+	txcmd_txdp = priv->FirstTxDesc << 13;
+	TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2);
+
+	OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD);
+
+	/* Comput access times */
+	count = (length + priv->PadSize) >> priv->BusWidth;
+
+	for (i = 0; i < count; i++) {
+		WRITE_TXBUF (dev, *(txdata + i));
+	}
+
+	OUTW (dev, txcmd_txdp | length, TXCMD);
+	OUTW (dev, txbs_txdp, TXBS);
+	OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr);
+
+	priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK;
+
+	/*
+	 * Check the available transmit descriptor, if we had exhausted all
+	 * transmit descriptor ,then we have to wait for at least one free
+	 * descriptor
+	 */
+	txbs_txdp = 1 << priv->NextTxDesc;
+	tmp_data = INW (dev, TXBS);
+
+	if (tmp_data & txbs_txdp) {
+		if (ax88180_poll_tx_complete (dev) < 0) {
+			ax88180_mac_reset (dev);
+			priv->FirstTxDesc = TXDP0;
+			priv->NextTxDesc = TXDP0;
+			printf ("ax88180: Transmit time out occurred!\n");
+		}
+	}
+
+	return 0;
+}
+
+static void ax88180_read_mac_addr (struct eth_device *dev)
+{
+	unsigned short macid0_val, macid1_val, macid2_val;
+	unsigned short tmp_regval;
+	unsigned short i;
+
+	/* Reload MAC address from EEPROM */
+	OUTW (dev, RELOAD_EEPROM, PROMCTRL);
+
+	/* Waiting for reload eeprom completion */
+	for (i = 0; i < 500; i++) {
+		tmp_regval = INW (dev, PROMCTRL);
+		if ((tmp_regval & RELOAD_EEPROM) == 0)
+			break;
+		udelay (1000);
+	}
+
+	/* Get MAC addresses */
+	macid0_val = INW (dev, MACID0);
+	macid1_val = INW (dev, MACID1);
+	macid2_val = INW (dev, MACID2);
+
+	if (((macid0_val | macid1_val | macid2_val) != 0) &&
+	    ((macid0_val & 0x01) == 0)) {
+		dev->enetaddr[0] = (unsigned char)macid0_val;
+		dev->enetaddr[1] = (unsigned char)(macid0_val >> 8);
+		dev->enetaddr[2] = (unsigned char)macid1_val;
+		dev->enetaddr[3] = (unsigned char)(macid1_val >> 8);
+		dev->enetaddr[4] = (unsigned char)macid2_val;
+		dev->enetaddr[5] = (unsigned char)(macid2_val >> 8);
+	}
+}
+
+/*
+===========================================================================
+<<<<<<			Exported SubProgram Bodies		>>>>>>
+===========================================================================
+*/
+int ax88180_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	struct ax88180_private *priv;
+
+	dev = (struct eth_device *)malloc (sizeof *dev);
+
+	if (NULL == dev)
+		return 0;
+
+	memset (dev, 0, sizeof *dev);
+
+	priv = (struct ax88180_private *)malloc (sizeof (*priv));
+
+	if (NULL == priv)
+		return 0;
+
+	memset (priv, 0, sizeof *priv);
+
+	sprintf (dev->name, "ax88180");
+	dev->iobase = AX88180_BASE;
+	dev->priv = priv;
+	dev->init = ax88180_init;
+	dev->halt = ax88180_halt;
+	dev->send = ax88180_send;
+	dev->recv = ax88180_recv;
+
+	priv->BusWidth = BUS_WIDTH_32;
+	priv->PadSize = 3;
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+	OUTW (dev, (START_BASE >> 8), BASE);
+	OUTW (dev, DECODE_EN, DECODE);
+
+	priv->BusWidth = BUS_WIDTH_16;
+	priv->PadSize = 1;
+#endif
+
+	ax88180_mac_reset (dev);
+
+	/* Disable interrupt */
+	OUTW (dev, CLEAR_IMR, IMR);
+
+	/* Disable AX88180 TX/RX functions */
+	OUTW (dev, WAKEMOD, CMD);
+
+	ax88180_read_mac_addr (dev);
+
+	eth_register (dev);
+
+	return ax88180_phy_initial (dev);
+
+}
diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h
new file mode 100644
index 0000000..d2113df
--- /dev/null
+++ b/drivers/net/ax88180.h
@@ -0,0 +1,412 @@
+/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
+/*
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#ifndef _AX88180_H_
+#define _AX88180_H_
+
+#include <asm/types.h>
+#include <config.h>
+
+typedef enum _ax88180_link_state {
+	INS_LINK_DOWN,
+	INS_LINK_UP,
+	INS_LINK_UNKNOWN
+} ax88180_link_state;
+
+struct ax88180_private {
+	unsigned char BusWidth;
+	unsigned char PadSize;
+	unsigned short PhyAddr;
+	unsigned short PhyID0;
+	unsigned short FirstTxDesc;
+	unsigned short NextTxDesc;
+	ax88180_link_state LinkState;
+};
+
+#define BUS_WIDTH_16			1
+#define BUS_WIDTH_32			2
+
+#define ENABLE_JUMBO			1
+#define DISABLE_JUMBO			0
+
+#define ENABLE_BURST			1
+#define DISABLE_BURST			0
+
+#define NORMAL_RX_MODE		0
+#define RX_LOOPBACK_MODE		1
+#define RX_INIFINIT_LOOP_MODE		2
+#define TX_INIFINIT_LOOP_MODE		3
+
+#define DEFAULT_ETH_MTU		1500
+
+/* Jumbo packet size 4086 bytes included 4 bytes CRC*/
+#define MAX_JUMBO_MTU		4072
+
+/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
+#define MAX_TX_JUMBO_SIZE		4086
+
+/* Max Rx Jumbo size is 15K Bytes */
+#define MAX_RX_SIZE			0x3C00
+
+#define MARVELL_88E1111_PHYADDR	0x18
+#define MARVELL_88E1111_PHYIDR0	0x0141
+
+#define CICADA_CIS8201_PHYADDR	0x01
+#define CICADA_CIS8201_PHYIDR0		0x000F
+
+#define MEDIA_AUTO			0
+#define MEDIA_1000FULL			1
+#define MEDIA_1000HALF			2
+#define MEDIA_100FULL			3
+#define MEDIA_100HALF			4
+#define MEDIA_10FULL			5
+#define MEDIA_10HALF			6
+#define MEDIA_UNKNOWN		7
+
+#define AUTO_MEDIA			0
+#define FORCE_MEDIA			1
+
+#define TXDP_MASK			3
+#define TXDP0				0
+#define TXDP1				1
+#define TXDP2				2
+#define TXDP3				3
+
+#define CMD_MAP_SIZE			0x100
+
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+  #define AX88180_MEMORY_SIZE		0x00004000
+  #define START_BASE			0x1000
+
+  #define RX_BUF_SIZE			0x1000
+  #define TX_BUF_SIZE			0x0F00
+
+  #define TX_BASE			START_BASE
+  #define CMD_BASE			(TX_BASE + TX_BUF_SIZE)
+  #define RX_BASE			(CMD_BASE + CMD_MAP_SIZE)
+#else
+  #define AX88180_MEMORY_SIZE	0x00010000
+
+  #define RX_BUF_SIZE			0x8000
+  #define TX_BUF_SIZE			0x7C00
+
+  #define RX_BASE			0x0000
+  #define TX_BASE			(RX_BASE + RX_BUF_SIZE)
+  #define CMD_BASE			(TX_BASE + TX_BUF_SIZE)
+#endif
+
+/* AX88180 Memory Mapping Definition */
+#define RXBUFFER_START			RX_BASE
+  #define RX_PACKET_LEN_OFFSET	0
+  #define RX_PAGE_NUM_MASK		0x7FF	/* RX pages 0~7FFh */
+#define TXBUFFER_START			TX_BASE
+
+/* AX88180 MAC Register Definition */
+#define DECODE		(0)
+  #define DECODE_EN		0x00000001
+#define BASE		(6)
+#define CMD		(CMD_BASE + 0x0000)
+  #define WAKEMOD		0x00000001
+  #define TXEN			0x00000100
+  #define RXEN			0x00000200
+  #define DEFAULT_CMD		WAKEMOD
+#define IMR		(CMD_BASE + 0x0004)
+  #define IMR_RXBUFFOVR	0x00000001
+  #define IMR_WATCHDOG	0x00000002
+  #define IMR_TX		0x00000008
+  #define IMR_RX		0x00000010
+  #define IMR_PHY		0x00000020
+  #define CLEAR_IMR		0x00000000
+  #define DEFAULT_IMR		(IMR_PHY | IMR_RX | IMR_TX |\
+					 IMR_RXBUFFOVR | IMR_WATCHDOG)
+#define ISR		(CMD_BASE + 0x0008)
+  #define ISR_RXBUFFOVR	0x00000001
+  #define ISR_WATCHDOG	0x00000002
+  #define ISR_TX			0x00000008
+  #define ISR_RX			0x00000010
+  #define ISR_PHY		0x00000020
+#define TXCFG		(CMD_BASE + 0x0010)
+  #define AUTOPAD_CRC		0x00000050
+  #define DEFAULT_TXCFG	AUTOPAD_CRC
+#define TXCMD		(CMD_BASE + 0x0014)
+  #define TXCMD_TXDP_MASK	0x00006000
+  #define TXCMD_TXDP0		0x00000000
+  #define TXCMD_TXDP1		0x00002000
+  #define TXCMD_TXDP2		0x00004000
+  #define TXCMD_TXDP3		0x00006000
+  #define TX_START_WRITE	0x00008000
+  #define TX_STOP_WRITE		0x00000000
+  #define DEFAULT_TXCMD	0x00000000
+#define TXBS		(CMD_BASE + 0x0018)
+  #define TXDP0_USED		0x00000001
+  #define TXDP1_USED		0x00000002
+  #define TXDP2_USED		0x00000004
+  #define TXDP3_USED		0x00000008
+  #define DEFAULT_TXBS		0x00000000
+#define TXDES0		(CMD_BASE + 0x0020)
+  #define TXDPx_ENABLE		0x00008000
+  #define TXDPx_LEN_MASK	0x00001FFF
+  #define DEFAULT_TXDES0	0x00000000
+#define TXDES1		(CMD_BASE + 0x0024)
+  #define TXDPx_ENABLE		0x00008000
+  #define TXDPx_LEN_MASK	0x00001FFF
+  #define DEFAULT_TXDES1	0x00000000
+#define TXDES2		(CMD_BASE + 0x0028)
+  #define TXDPx_ENABLE		0x00008000
+  #define TXDPx_LEN_MASK	0x00001FFF
+  #define DEFAULT_TXDES2	0x00000000
+#define TXDES3		(CMD_BASE + 0x002C)
+  #define TXDPx_ENABLE		0x00008000
+  #define TXDPx_LEN_MASK	0x00001FFF
+  #define DEFAULT_TXDES3	0x00000000
+#define RXCFG		(CMD_BASE + 0x0030)
+  #define RXBUFF_PROTECT	0x00000001
+  #define RXTCPCRC_CHECK	0x00000010
+  #define RXFLOW_ENABLE	0x00000100
+  #define DEFAULT_RXCFG	RXBUFF_PROTECT
+#define RXCURT		(CMD_BASE + 0x0034)
+  #define DEFAULT_RXCURT	0x00000000
+#define RXBOUND	(CMD_BASE + 0x0038)
+  #define DEFAULT_RXBOUND	0x7FF		/* RX pages 0~7FFh */
+#define MACCFG0	(CMD_BASE + 0x0040)
+  #define MACCFG0_BIT3_0	0x00000007
+  #define IPGT_VAL		0x00000150
+  #define TXFLOW_ENABLE	0x00001000
+  #define SPEED100		0x00008000
+  #define DEFAULT_MACCFG0	(IPGT_VAL | MACCFG0_BIT3_0)
+#define MACCFG1	(CMD_BASE + 0x0044)
+  #define RGMII_EN		0x00000002
+  #define RXFLOW_EN		0x00000020
+  #define FULLDUPLEX		0x00000040
+  #define MAX_JUMBO_LEN	0x00000780
+  #define RXJUMBO_EN		0x00000800
+  #define GIGA_MODE_EN	0x00001000
+  #define RXCRC_CHECK		0x00002000
+  #define RXPAUSE_DA_CHECK	0x00004000
+
+  #define JUMBO_LEN_4K		0x00000200
+  #define JUMBO_LEN_15K	0x00000780
+  #define DEFAULT_MACCFG1	(RXCRC_CHECK | RXPAUSE_DA_CHECK | \
+				 RGMII_EN)
+  #define CICADA_DEFAULT_MACCFG1	(RXCRC_CHECK | RXPAUSE_DA_CHECK)
+#define MACCFG2		(CMD_BASE + 0x0048)
+  #define MACCFG2_BIT15_8	0x00000100
+  #define JAM_LIMIT_MASK	0x000000FC
+  #define DEFAULT_JAM_LIMIT	0x00000064
+  #define DEFAULT_MACCFG2	MACCFG2_BIT15_8
+#define MACCFG3		(CMD_BASE + 0x004C)
+  #define IPGR2_VAL		0x0000000E
+  #define IPGR1_VAL		0x00000600
+  #define NOABORT		0x00008000
+  #define DEFAULT_MACCFG3	(IPGR1_VAL | IPGR2_VAL)
+#define TXPAUT		(CMD_BASE + 0x0054)
+  #define DEFAULT_TXPAUT	0x001FE000
+#define RXBTHD0		(CMD_BASE + 0x0058)
+  #define DEFAULT_RXBTHD0	0x00000300
+#define RXBTHD1		(CMD_BASE + 0x005C)
+  #define DEFAULT_RXBTHD1	0x00000600
+#define RXFULTHD	(CMD_BASE + 0x0060)
+  #define DEFAULT_RXFULTHD	0x00000100
+#define MISC		(CMD_BASE + 0x0068)
+  /* Normal operation mode */
+  #define MISC_NORMAL		0x00000003
+  /* Clear bit 0 to reset MAC */
+  #define MISC_RESET_MAC	0x00000002
+  /* Clear bit 1 to reset PHY */
+  #define MISC_RESET_PHY	0x00000001
+  /* Clear bit 0 and 1 to reset MAC and PHY */
+  #define MISC_RESET_MAC_PHY	0x00000000
+  #define DEFAULT_MISC		MISC_NORMAL
+#define MACID0		(CMD_BASE + 0x0070)
+#define MACID1		(CMD_BASE + 0x0074)
+#define MACID2		(CMD_BASE + 0x0078)
+#define TXLEN		(CMD_BASE + 0x007C)
+  #define DEFAULT_TXLEN	0x000005FC
+#define RXFILTER	(CMD_BASE + 0x0080)
+  #define RX_RXANY		0x00000001
+  #define RX_MULTICAST		0x00000002
+  #define RX_UNICAST		0x00000004
+  #define RX_BROADCAST	0x00000008
+  #define RX_MULTI_HASH	0x00000010
+  #define DISABLE_RXFILTER	0x00000000
+  #define DEFAULT_RXFILTER	(RX_BROADCAST + RX_UNICAST)
+#define MDIOCTRL	(CMD_BASE + 0x0084)
+  #define PHY_ADDR_MASK	0x0000001F
+  #define REG_ADDR_MASK	0x00001F00
+  #define READ_PHY		0x00004000
+  #define WRITE_PHY		0x00008000
+#define MDIODP		(CMD_BASE + 0x0088)
+#define GPIOCTRL	(CMD_BASE + 0x008C)
+#define RXINDICATOR	(CMD_BASE + 0x0090)
+  #define RX_START_READ	0x00000001
+  #define RX_STOP_READ		0x00000000
+  #define DEFAULT_RXINDICATOR	RX_STOP_READ
+#define TXST		(CMD_BASE + 0x0094)
+#define MDCCLKPAT	(CMD_BASE + 0x00A0)
+#define RXIPCRCCNT	(CMD_BASE + 0x00A4)
+#define RXCRCCNT	(CMD_BASE + 0x00A8)
+#define TXFAILCNT	(CMD_BASE + 0x00AC)
+#define PROMDP		(CMD_BASE + 0x00B0)
+#define PROMCTRL	(CMD_BASE + 0x00B4)
+  #define RELOAD_EEPROM	0x00000200
+#define MAXRXLEN	(CMD_BASE + 0x00B8)
+#define HASHTAB0	(CMD_BASE + 0x00C0)
+#define HASHTAB1	(CMD_BASE + 0x00C4)
+#define HASHTAB2	(CMD_BASE + 0x00C8)
+#define HASHTAB3	(CMD_BASE + 0x00CC)
+#define DOGTHD0	(CMD_BASE + 0x00E0)
+  #define DEFAULT_DOGTHD0	0x0000FFFF
+#define DOGTHD1	(CMD_BASE + 0x00E4)
+  #define START_WATCHDOG_TIMER	0x00008000
+  #define DEFAULT_DOGTHD1		0x00000FFF
+#define SOFTRST		(CMD_BASE + 0x00EC)
+  #define SOFTRST_NORMAL	0x00000003
+  #define SOFTRST_RESET_MAC	0x00000002
+
+/* External PHY Register Definition */
+#define BMCR		0x0000
+  #define LINE_SPEED_MSB	0x0040
+  #define DUPLEX_MODE		0x0100
+  #define RESTART_AUTONEG	0x0200
+  #define POWER_DOWN		0x0800
+  #define AUTONEG_EN		0x1000
+  #define LINE_SPEED_LSB	0x2000
+  #define PHY_RESET		0x8000
+
+  #define MEDIAMODE_MASK	(LINE_SPEED_MSB | LINE_SPEED_LSB |\
+				 DUPLEX_MODE)
+  #define BMCR_SPEED_1000	LINE_SPEED_MSB
+  #define BMCR_SPEED_100	LINE_SPEED_LSB
+  #define BMCR_SPEED_10	0x0000
+
+  #define BMCR_1000FULL	(BMCR_SPEED_1000 | DUPLEX_MODE)
+  #define BMCR_100FULL		(BMCR_SPEED_100 | DUPLEX_MODE)
+  #define BMCR_100HALF		BMCR_SPEED_100
+  #define BMCR_10FULL		DUPLEX_MODE
+  #define BMCR_10HALF		0x0000
+#define BMSR		0x0001
+  #define LINKOK		0x0004
+  #define AUTONEG_ENABLE_STS	0x0008
+  #define AUTONEG_COMPLETE	0x0020
+#define PHYIDR0		0x0002
+#define PHYIDR1		0x0003
+#define ANAR		0x0004
+  #define ANAR_PAUSE		0x0400
+  #define ANAR_100FULL		0x0100
+  #define ANAR_100HALF		0x0080
+  #define ANAR_10FULL		0x0040
+  #define ANAR_10HALF		0x0020
+  #define ANAR_8023BIT		0x0001
+#define ANLPAR		0x0005
+#define ANER		0x0006
+#define AUX_1000_CTRL	0x0009
+  #define ENABLE_1000HALF	0x0100
+  #define ENABLE_1000FULL	0x0200
+  #define DEFAULT_AUX_1000_CTRL	(ENABLE_1000HALF | ENABLE_1000FULL)
+#define AUX_1000_STATUS	0x000A
+  #define LP_1000HALF		0x0400
+  #define LP_1000FULL		0x0800
+
+/* Marvell 88E1111 Gigabit PHY Register Definition */
+#define M88_SSR		0x0011
+  #define SSR_SPEED_MASK	0xC000
+  #define SSR_SPEED_1000		0x8000
+  #define SSR_SPEED_100		0x4000
+  #define SSR_SPEED_10		0x0000
+  #define SSR_DUPLEX		0x2000
+  #define SSR_MEDIA_RESOLVED_OK	0x0800
+
+  #define SSR_MEDIA_MASK	(SSR_SPEED_MASK | SSR_DUPLEX)
+  #define SSR_1000FULL		(SSR_SPEED_1000 | SSR_DUPLEX)
+  #define SSR_1000HALF		SSR_SPEED_1000
+  #define SSR_100FULL		(SSR_SPEED_100 | SSR_DUPLEX)
+  #define SSR_100HALF		SSR_SPEED_100
+  #define SSR_10FULL		(SSR_SPEED_10 | SSR_DUPLEX)
+  #define SSR_10HALF		SSR_SPEED_10
+#define M88_IER		0x0012
+  #define LINK_CHANGE_INT	0x0400
+#define M88_ISR		0x0013
+  #define LINK_CHANGE_STATUS	0x0400
+#define M88_EXT_SCR	0x0014
+  #define RGMII_RXCLK_DELAY	0x0080
+  #define RGMII_TXCLK_DELAY	0x0002
+  #define DEFAULT_EXT_SCR	(RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
+#define M88_EXT_SSR	0x001B
+  #define HWCFG_MODE_MASK	0x000F
+  #define RGMII_COPPER_MODE	0x000B
+
+/* CICADA CIS8201 Gigabit PHY Register Definition */
+#define CIS_IMR		0x0019
+  #define CIS_INT_ENABLE	0x8000
+  #define CIS_LINK_CHANGE_INT	0x2000
+#define CIS_ISR		0x001A
+  #define CIS_INT_PENDING	0x8000
+  #define CIS_LINK_CHANGE_STATUS	0x2000
+#define CIS_AUX_CTRL_STATUS	0x001C
+  #define CIS_AUTONEG_COMPLETE	0x8000
+  #define CIS_SPEED_MASK	0x0018
+  #define CIS_SPEED_1000		0x0010
+  #define CIS_SPEED_100		0x0008
+  #define CIS_SPEED_10		0x0000
+  #define CIS_DUPLEX		0x0020
+
+  #define CIS_MEDIA_MASK	(CIS_SPEED_MASK | CIS_DUPLEX)
+  #define CIS_1000FULL		(CIS_SPEED_1000 | CIS_DUPLEX)
+  #define CIS_1000HALF		CIS_SPEED_1000
+  #define CIS_100FULL		(CIS_SPEED_100 | CIS_DUPLEX)
+  #define CIS_100HALF		CIS_SPEED_100
+  #define CIS_10FULL		(CIS_SPEED_10 | CIS_DUPLEX)
+  #define CIS_10HALF		CIS_SPEED_10
+  #define CIS_SMI_PRIORITY	0x0004
+
+static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
+{
+	return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase));
+}
+
+static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
+{
+	*(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command);
+}
+
+/*
+ Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
+*/
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+static inline unsigned short READ_RXBUF (struct eth_device *dev)
+{
+	return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase));
+}
+
+static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
+{
+	*(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data);
+}
+#else
+static inline unsigned long READ_RXBUF (struct eth_device *dev)
+{
+	return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase));
+}
+
+static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
+{
+	*(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data);
+}
+#endif
+
+#endif /* _AX88180_H_ */
diff --git a/drivers/net/ax88796.c b/drivers/net/ax88796.c
index 39cd101..2089141 100644
--- a/drivers/net/ax88796.c
+++ b/drivers/net/ax88796.c
@@ -143,7 +143,7 @@ static void ax88796_mac_read(u8 *buff)
 	}
 }
 
-int get_prom(u8* mac_addr)
+int get_prom(u8* mac_addr, u8* base_addr)
 {
 	u8 prom[32];
 	int i;
diff --git a/drivers/net/bcm570x.c b/drivers/net/bcm570x.c
index 6b28b95..185764e 100644
--- a/drivers/net/bcm570x.c
+++ b/drivers/net/bcm570x.c
@@ -439,9 +439,9 @@ int eth_init (bd_t * bis)
 	/* Setup timer delays */
 	if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
 		pDevice->UseTaggedStatus = TRUE;
-		pUmDevice->timer_interval = CFG_HZ;
+		pUmDevice->timer_interval = CONFIG_SYS_HZ;
 	} else {
-		pUmDevice->timer_interval = CFG_HZ / 50;
+		pUmDevice->timer_interval = CONFIG_SYS_HZ / 50;
 	}
 
 	/* Grab name .... */
@@ -458,15 +458,15 @@ int eth_init (bd_t * bis)
 	pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
 
 	/* delay for 4 seconds */
-	pUmDevice->delayed_link_ind = (4 * CFG_HZ) / pUmDevice->timer_interval;
+	pUmDevice->delayed_link_ind = (4 * CONFIG_SYS_HZ) / pUmDevice->timer_interval;
 
-	pUmDevice->adaptive_expiry = CFG_HZ / pUmDevice->timer_interval;
+	pUmDevice->adaptive_expiry = CONFIG_SYS_HZ / pUmDevice->timer_interval;
 
 	/* Sometimes we get spurious ints. after reset when link is down. */
 	/* This field tells the isr to service the int. even if there is */
 	/* no status block update. */
 	pUmDevice->adapter_just_inited =
-	    (3 * CFG_HZ) / pUmDevice->timer_interval;
+	    (3 * CONFIG_SYS_HZ) / pUmDevice->timer_interval;
 
 	/* Initialize 570x */
 	if (LM_InitializeAdapter (pDevice) != LM_STATUS_SUCCESS) {
@@ -1046,9 +1046,9 @@ LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice)
 
 	if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
 		pDevice->UseTaggedStatus = TRUE;
-		pUmDevice->timer_interval = CFG_HZ;
+		pUmDevice->timer_interval = CONFIG_SYS_HZ;
 	} else {
-		pUmDevice->timer_interval = CFG_HZ / 50;
+		pUmDevice->timer_interval = CONFIG_SYS_HZ / 50;
 	}
 
 	pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index 3ee5d96..504fd10 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <config.h>
 #include <net.h>
+#include <netdev.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -465,7 +466,7 @@ ADI_ETHER_BUFFER *SetupTxBuffer(int no)
 	return buf;
 }
 
-#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
+#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
 int ether_post_test(int flags)
 {
 	uchar buf[64];
diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c
index ae1983a..35a9baf 100644
--- a/drivers/net/cs8900.c
+++ b/drivers/net/cs8900.c
@@ -90,7 +90,7 @@ static void eth_reset (void)
 	udelay (200000);
 	/* Wait until the chip is reset */
 
-	tmo = get_timer (0) + 1 * CFG_HZ;
+	tmo = get_timer (0) + 1 * CONFIG_SYS_HZ;
 	while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0)
 		   && tmo < get_timer (0))
 		/*NOP*/;
@@ -244,7 +244,7 @@ retry:
 #ifdef DEBUG
 		printf ("cs: unable to send packet; retrying...\n");
 #endif
-		for (tmo = get_timer (0) + 5 * CFG_HZ; get_timer (0) < tmo;)
+		for (tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; get_timer (0) < tmo;)
 			/*NOP*/;
 		eth_reset ();
 		eth_reginit ();
@@ -257,7 +257,7 @@ retry:
 		CS8900_RTDATA = *addr++;
 
 	/* wait for transfer to succeed */
-	tmo = get_timer (0) + 5 * CFG_HZ;
+	tmo = get_timer (0) + 5 * CONFIG_SYS_HZ;
 	while ((s = get_reg (PP_TER) & ~0x1F) == 0) {
 		if (get_timer (0) >= tmo)
 			break;
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index 8117239..c0137a7 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -21,6 +21,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <pci.h>
 
 #undef DEBUG_SROM
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index 3a61b80..ffb739d 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -447,7 +447,7 @@ eth_send(volatile void *packet, int length)
 	DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
 
 	/* wait for end of transmission */
-	tmo = get_timer(0) + 5 * CFG_HZ;
+	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
 	while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
 		!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
 		if (get_timer(0) >= tmo) {
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index c8b4e98..2dcaa2c 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -3059,5 +3059,5 @@ e1000_initialize(bd_t * bis)
 
 		card_number++;
 	}
-	return 1;
+	return card_number;
 }
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index c258bc2..08042a8 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -36,6 +36,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index 9de0fb5..9c06b25 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -24,6 +24,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 #include <miiphy.h>
@@ -193,14 +194,14 @@ struct descriptor {			/* A generic descriptor. */
 	unsigned char params[0];
 };
 
-#define CFG_CMD_EL		0x8000
-#define CFG_CMD_SUSPEND		0x4000
-#define CFG_CMD_INT		0x2000
-#define CFG_CMD_IAS		0x0001	/* individual address setup */
-#define CFG_CMD_CONFIGURE	0x0002	/* configure */
+#define CONFIG_SYS_CMD_EL		0x8000
+#define CONFIG_SYS_CMD_SUSPEND		0x4000
+#define CONFIG_SYS_CMD_INT		0x2000
+#define CONFIG_SYS_CMD_IAS		0x0001	/* individual address setup */
+#define CONFIG_SYS_CMD_CONFIGURE	0x0002	/* configure */
 
-#define CFG_STATUS_C		0x8000
-#define CFG_STATUS_OK		0x2000
+#define CONFIG_SYS_STATUS_C		0x8000
+#define CONFIG_SYS_STATUS_OK		0x2000
 
 	/* Misc.
 	 */
@@ -528,7 +529,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis)
 	tx_next = ((tx_next + 1) % NUM_TX_DESC);
 
 	cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
-	cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE));
+	cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
 	cfg_cmd->status = 0;
 	cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
 
@@ -536,7 +537,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis)
 			sizeof (i82558_config_cmd));
 
 	if (!wait_for_eepro100 (dev)) {
-		printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n");
+		printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
 		goto Done;
 	}
 
@@ -544,7 +545,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis)
 	OUTW (dev, SCB_M | CU_START, SCBCmd);
 
 	for (i = 0;
-	     !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
+	     !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
 	     i++) {
 		if (i >= TOUT_LOOP) {
 			printf ("%s: Tx error buffer not ready\n", dev->name);
@@ -552,7 +553,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis)
 		}
 	}
 
-	if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
+	if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
 		printf ("TX error status = 0x%08X\n",
 			le16_to_cpu (tx_ring[tx_cur].status));
 		goto Done;
@@ -564,7 +565,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis)
 	tx_next = ((tx_next + 1) % NUM_TX_DESC);
 
 	ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
-	ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS));
+	ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
 	ias_cmd->status = 0;
 	ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
 
@@ -580,7 +581,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis)
 	OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
 	OUTW (dev, SCB_M | CU_START, SCBCmd);
 
-	for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
+	for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
 		 i++) {
 		if (i >= TOUT_LOOP) {
 			printf ("%s: Tx error buffer not ready\n",
@@ -589,7 +590,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis)
 		}
 	}
 
-	if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
+	if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
 		printf ("TX error status = 0x%08X\n",
 			le16_to_cpu (tx_ring[tx_cur].status));
 		goto Done;
@@ -639,7 +640,7 @@ static int eepro100_send (struct eth_device *dev, volatile void *packet, int len
 	OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
 	OUTW (dev, SCB_M | CU_START, SCBCmd);
 
-	for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
+	for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
 		 i++) {
 		if (i >= TOUT_LOOP) {
 			printf ("%s: Tx error buffer not ready\n", dev->name);
@@ -647,7 +648,7 @@ static int eepro100_send (struct eth_device *dev, volatile void *packet, int len
 		}
 	}
 
-	if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
+	if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
 		printf ("TX error status = 0x%08X\n",
 			le16_to_cpu (tx_ring[tx_cur].status));
 		goto Done;
diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
index 59524a5..d056010 100644
--- a/drivers/net/fsl_mcdmafec.c
+++ b/drivers/net/fsl_mcdmafec.c
@@ -56,12 +56,12 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct fec_info_dma fec_info[] = {
-#ifdef CFG_FEC0_IOBASE
+#ifdef CONFIG_SYS_FEC0_IOBASE
 	{
 	 0,			/* index */
-	 CFG_FEC0_IOBASE,	/* io base */
-	 CFG_FEC0_PINMUX,	/* gpio pin muxing */
-	 CFG_FEC0_MIIBASE,	/* mii base */
+	 CONFIG_SYS_FEC0_IOBASE,	/* io base */
+	 CONFIG_SYS_FEC0_PINMUX,	/* gpio pin muxing */
+	 CONFIG_SYS_FEC0_MIIBASE,	/* mii base */
 	 -1,			/* phy_addr */
 	 0,			/* duplex and speed */
 	 0,			/* phy name */
@@ -83,17 +83,17 @@ struct fec_info_dma fec_info[] = {
 	 0,			/* cleanTbdNum */
 	 },
 #endif
-#ifdef CFG_FEC1_IOBASE
+#ifdef CONFIG_SYS_FEC1_IOBASE
 	{
 	 1,			/* index */
-	 CFG_FEC1_IOBASE,	/* io base */
-	 CFG_FEC1_PINMUX,	/* gpio pin muxing */
-	 CFG_FEC1_MIIBASE,	/* mii base */
+	 CONFIG_SYS_FEC1_IOBASE,	/* io base */
+	 CONFIG_SYS_FEC1_PINMUX,	/* gpio pin muxing */
+	 CONFIG_SYS_FEC1_MIIBASE,	/* mii base */
 	 -1,			/* phy_addr */
 	 0,			/* duplex and speed */
 	 0,			/* phy name */
 	 0,			/* phy name init */
-#ifdef CFG_DMA_USE_INTSRAM
+#ifdef CONFIG_SYS_DMA_USE_INTSRAM
 	 (cbd_t *)DBUF_LENGTH,	/* RX BD */
 #else
 	 0,			/* RX BD */
@@ -203,7 +203,7 @@ static int fec_send(struct eth_device *dev, volatile void *packet, int length)
 	miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
 
 	/* process all the consumed TBDs */
-	while (info->cleanTbdNum < CFG_TX_ETH_BUFFER) {
+	while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
 		pUsedTbd = &info->txbd[info->usedTbdIdx];
 		if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
 #ifdef ET_DEBUG
@@ -214,14 +214,14 @@ static int fec_send(struct eth_device *dev, volatile void *packet, int length)
 		}
 
 		/* clean this buffer descriptor */
-		if (info->usedTbdIdx == (CFG_TX_ETH_BUFFER - 1))
+		if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
 			pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
 		else
 			pUsedTbd->cbd_sc = 0;
 
 		/* update some indeces for a correct handling of the TBD ring */
 		info->cleanTbdNum++;
-		info->usedTbdIdx = (info->usedTbdIdx + 1) % CFG_TX_ETH_BUFFER;
+		info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
 	}
 
 	/* Check for valid length of data. */
@@ -240,7 +240,7 @@ static int fec_send(struct eth_device *dev, volatile void *packet, int length)
 	pTbd->cbd_datlen = length;
 	pTbd->cbd_bufaddr = (u32) packet;
 	pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
-	info->txIdx = (info->txIdx + 1) % CFG_TX_ETH_BUFFER;
+	info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
 
 	/* Enable DMA transmit task */
 	MCD_continDma(info->txTask);
@@ -379,15 +379,15 @@ static int fec_init(struct eth_device *dev, bd_t * bd)
 	fec_halt(dev);
 
 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
-	defined (CFG_DISCOVER_PHY)
+	defined (CONFIG_SYS_DISCOVER_PHY)
 
 	mii_init();
 
 	set_fec_duplex_speed(fecp, bd, info->dup_spd);
 #else
-#ifndef CFG_DISCOVER_PHY
+#ifndef CONFIG_SYS_DISCOVER_PHY
 	set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
-#endif				/* ifndef CFG_DISCOVER_PHY */
+#endif				/* ifndef CONFIG_SYS_DISCOVER_PHY */
 #endif				/* CONFIG_CMD_MII || CONFIG_MII */
 
 	/* We use strictly polling mode only */
@@ -397,7 +397,7 @@ static int fec_init(struct eth_device *dev, bd_t * bd)
 	fecp->eir = 0xffffffff;
 
 	/* Set station address   */
-	if ((u32) fecp == CFG_FEC0_IOBASE) {
+	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
 		fec_set_hwaddr(fecp, bd->bi_enetaddr);
 	} else {
 		fec_set_hwaddr(fecp, bd->bi_enet1addr);
@@ -421,15 +421,15 @@ static int fec_init(struct eth_device *dev, bd_t * bd)
 
 	/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
 	 * Settings:    Last, Tx CRC */
-	for (i = 0; i < CFG_TX_ETH_BUFFER; i++) {
+	for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
 		info->txbd[i].cbd_sc = 0;
 		info->txbd[i].cbd_datlen = 0;
 		info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
 	}
-	info->txbd[CFG_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
+	info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
 
 	info->usedTbdIdx = 0;
-	info->cleanTbdNum = CFG_TX_ETH_BUFFER;
+	info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
 
 	/* Set Rx FIFO alarm and granularity value */
 	fecp->rfcr = 0x0c000000;
@@ -516,14 +516,14 @@ int mcdmafec_initialize(bd_t * bis)
 {
 	struct eth_device *dev;
 	int i;
-#ifdef CFG_DMA_USE_INTSRAM
-	u32 tmp = CFG_INTSRAM + 0x2000;
+#ifdef CONFIG_SYS_DMA_USE_INTSRAM
+	u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
 #endif
 
 	for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
 
 		dev =
-		    (struct eth_device *)memalign(CFG_CACHELINE_SIZE,
+		    (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
 						  sizeof *dev);
 		if (dev == NULL)
 			hang();
@@ -539,7 +539,7 @@ int mcdmafec_initialize(bd_t * bis)
 		dev->recv = fec_recv;
 
 		/* setup Receive and Transmit buffer descriptor */
-#ifdef CFG_DMA_USE_INTSRAM
+#ifdef CONFIG_SYS_DMA_USE_INTSRAM
 		fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
 		tmp = (u32)fec_info[i].rxbd;
 		fec_info[i].txbd =
@@ -548,17 +548,17 @@ int mcdmafec_initialize(bd_t * bis)
 		tmp = (u32)fec_info[i].txbd;
 		fec_info[i].txbuf =
 		    (char *)((u32)fec_info[i].txbuf + tmp +
-		    (CFG_TX_ETH_BUFFER * sizeof(cbd_t)));
+		    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
 		tmp = (u32)fec_info[i].txbuf;
 #else
 		fec_info[i].rxbd =
-		    (cbd_t *) memalign(CFG_CACHELINE_SIZE,
+		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
 				       (PKTBUFSRX * sizeof(cbd_t)));
 		fec_info[i].txbd =
-		    (cbd_t *) memalign(CFG_CACHELINE_SIZE,
-				       (CFG_TX_ETH_BUFFER * sizeof(cbd_t)));
+		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
+				       (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
 		fec_info[i].txbuf =
-		    (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
+		    (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
 #endif
 
 #ifdef ET_DEBUG
@@ -566,7 +566,7 @@ int mcdmafec_initialize(bd_t * bis)
 		       (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
 #endif
 
-		fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
+		fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
 
 		eth_register(dev);
 
diff --git a/drivers/net/greth.c b/drivers/net/greth.c
index 90c5338..79bc4d9 100644
--- a/drivers/net/greth.c
+++ b/drivers/net/greth.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <command.h>
 #include <net.h>
+#include <netdev.h>
 #include <malloc.h>
 #include <asm/processor.h>
 #include <ambapp.h>
diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c
index d852a15..492f5ce 100644
--- a/drivers/net/inca-ip_sw.c
+++ b/drivers/net/inca-ip_sw.c
@@ -28,6 +28,7 @@
 
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/inca-ip.h>
 #include <asm/addrspace.h>
 
@@ -199,7 +200,7 @@ int inca_switch_initialize(bd_t * bis)
 	printf("Leaving inca_switch_initialize()\n");
 #endif
 
-	return 1;
+	return 0;
 }
 
 
diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c
index c23a400..318bdf4 100644
--- a/drivers/net/lan91c96.c
+++ b/drivers/net/lan91c96.c
@@ -267,7 +267,7 @@ static void smc_shutdown (void);
 
 static int poll4int (byte mask, int timeout)
 {
-	int tmo = get_timer (0) + timeout * CFG_HZ;
+	int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
 	int is_timeout = 0;
 	word old_bank = SMC_inw (LAN91C96_BANK_SELECT);
 
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index aa39284..98e8c73 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -28,7 +28,7 @@
  * allocate our own, but we need one such buffer in case a packet
  * wraps around the DMA ring so that we have to copy it.
  *
- * Therefore, define CFG_RX_ETH_BUFFER to 1 in the board-specific
+ * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
  * configuration header.  This way, the core allocates one RX buffer
  * and one TX buffer, each of which can hold a ethernet packet of
  * maximum size.
@@ -40,6 +40,7 @@
  */
 
 #include <net.h>
+#include <netdev.h>
 #include <malloc.h>
 
 #include <linux/mii.h>
@@ -51,11 +52,11 @@
 
 #define barrier() asm volatile("" ::: "memory")
 
-#define CFG_MACB_RX_BUFFER_SIZE		4096
-#define CFG_MACB_RX_RING_SIZE		(CFG_MACB_RX_BUFFER_SIZE / 128)
-#define CFG_MACB_TX_RING_SIZE		16
-#define CFG_MACB_TX_TIMEOUT		1000
-#define CFG_MACB_AUTONEG_TIMEOUT	5000000
+#define CONFIG_SYS_MACB_RX_BUFFER_SIZE		4096
+#define CONFIG_SYS_MACB_RX_RING_SIZE		(CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
+#define CONFIG_SYS_MACB_TX_RING_SIZE		16
+#define CONFIG_SYS_MACB_TX_TIMEOUT		1000
+#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT	5000000
 
 struct macb_dma_desc {
 	u32	addr;
@@ -177,7 +178,7 @@ static int macb_send(struct eth_device *netdev, volatile void *packet,
 
 	ctrl = length & TXBUF_FRMLEN_MASK;
 	ctrl |= TXBUF_FRAME_END;
-	if (tx_head == (CFG_MACB_TX_RING_SIZE - 1)) {
+	if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) {
 		ctrl |= TXBUF_WRAP;
 		macb->tx_head = 0;
 	} else
@@ -192,7 +193,7 @@ static int macb_send(struct eth_device *netdev, volatile void *packet,
 	 * I guess this is necessary because the networking core may
 	 * re-use the transmit buffer as soon as we return...
 	 */
-	for (i = 0; i <= CFG_MACB_TX_TIMEOUT; i++) {
+	for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) {
 		barrier();
 		ctrl = macb->tx_ring[tx_head].ctrl;
 		if (ctrl & TXBUF_USED)
@@ -202,7 +203,7 @@ static int macb_send(struct eth_device *netdev, volatile void *packet,
 
 	dma_unmap_single(packet, length, paddr);
 
-	if (i <= CFG_MACB_TX_TIMEOUT) {
+	if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) {
 		if (ctrl & TXBUF_UNDERRUN)
 			printf("%s: TX underrun\n", netdev->name);
 		if (ctrl & TXBUF_EXHAUSTED)
@@ -225,7 +226,7 @@ static void reclaim_rx_buffers(struct macb_device *macb,
 	while (i > new_tail) {
 		macb->rx_ring[i].addr &= ~RXADDR_USED;
 		i++;
-		if (i > CFG_MACB_RX_RING_SIZE)
+		if (i > CONFIG_SYS_MACB_RX_RING_SIZE)
 			i = 0;
 	}
 
@@ -264,7 +265,7 @@ static int macb_recv(struct eth_device *netdev)
 			if (wrapped) {
 				unsigned int headlen, taillen;
 
-				headlen = 128 * (CFG_MACB_RX_RING_SIZE
+				headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE
 						 - macb->rx_tail);
 				taillen = length - headlen;
 				memcpy((void *)NetRxPackets[0],
@@ -275,11 +276,11 @@ static int macb_recv(struct eth_device *netdev)
 			}
 
 			NetReceive(buffer, length);
-			if (++rx_tail >= CFG_MACB_RX_RING_SIZE)
+			if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE)
 				rx_tail = 0;
 			reclaim_rx_buffers(macb, rx_tail);
 		} else {
-			if (++rx_tail >= CFG_MACB_RX_RING_SIZE) {
+			if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) {
 				wrapped = 1;
 				rx_tail = 0;
 			}
@@ -302,7 +303,7 @@ static void macb_phy_reset(struct macb_device *macb)
 	macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
 					 | BMCR_ANRESTART));
 
-	for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
+	for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
 		status = macb_mdio_read(macb, MII_BMSR);
 		if (status & BMSR_ANEGCOMPLETE)
 			break;
@@ -336,7 +337,7 @@ static int macb_phy_init(struct macb_device *macb)
 		/* Try to re-negotiate if we don't have link already. */
 		macb_phy_reset(macb);
 
-		for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
+		for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
 			status = macb_mdio_read(macb, MII_BMSR);
 			if (status & BMSR_LSTATUS)
 				break;
@@ -387,16 +388,16 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 
 	/* initialize DMA descriptors */
 	paddr = macb->rx_buffer_dma;
-	for (i = 0; i < CFG_MACB_RX_RING_SIZE; i++) {
-		if (i == (CFG_MACB_RX_RING_SIZE - 1))
+	for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) {
+		if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1))
 			paddr |= RXADDR_WRAP;
 		macb->rx_ring[i].addr = paddr;
 		macb->rx_ring[i].ctrl = 0;
 		paddr += 128;
 	}
-	for (i = 0; i < CFG_MACB_TX_RING_SIZE; i++) {
+	for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) {
 		macb->tx_ring[i].addr = 0;
-		if (i == (CFG_MACB_TX_RING_SIZE - 1))
+		if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1))
 			macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
 		else
 			macb->tx_ring[i].ctrl = TXBUF_USED;
@@ -472,12 +473,12 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 
 	netdev = &macb->netdev;
 
-	macb->rx_buffer = dma_alloc_coherent(CFG_MACB_RX_BUFFER_SIZE,
+	macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE,
 					     &macb->rx_buffer_dma);
-	macb->rx_ring = dma_alloc_coherent(CFG_MACB_RX_RING_SIZE
+	macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE
 					   * sizeof(struct macb_dma_desc),
 					   &macb->rx_ring_dma);
-	macb->tx_ring = dma_alloc_coherent(CFG_MACB_TX_RING_SIZE
+	macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE
 					   * sizeof(struct macb_dma_desc),
 					   &macb->tx_ring_dma);
 
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 50d6508..18240a8 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -27,13 +27,14 @@
 #include <common.h>
 #include <malloc.h>
 
-#include <asm/fec.h>
-#include <asm/immap.h>
-
 #include <command.h>
 #include <net.h>
+#include <netdev.h>
 #include <miiphy.h>
 
+#include <asm/fec.h>
+#include <asm/immap.h>
+
 #undef	ET_DEBUG
 #undef	MII_DEBUG
 
@@ -50,12 +51,12 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct fec_info_s fec_info[] = {
-#ifdef CFG_FEC0_IOBASE
+#ifdef CONFIG_SYS_FEC0_IOBASE
 	{
 	 0,			/* index */
-	 CFG_FEC0_IOBASE,	/* io base */
-	 CFG_FEC0_PINMUX,	/* gpio pin muxing */
-	 CFG_FEC0_MIIBASE,	/* mii base */
+	 CONFIG_SYS_FEC0_IOBASE,	/* io base */
+	 CONFIG_SYS_FEC0_PINMUX,	/* gpio pin muxing */
+	 CONFIG_SYS_FEC0_MIIBASE,	/* mii base */
 	 -1,			/* phy_addr */
 	 0,			/* duplex and speed */
 	 0,			/* phy name */
@@ -69,17 +70,17 @@ struct fec_info_s fec_info[] = {
 	 (struct fec_info_s *)-1,
 	 },
 #endif
-#ifdef CFG_FEC1_IOBASE
+#ifdef CONFIG_SYS_FEC1_IOBASE
 	{
 	 1,			/* index */
-	 CFG_FEC1_IOBASE,	/* io base */
-	 CFG_FEC1_PINMUX,	/* gpio pin muxing */
-	 CFG_FEC1_MIIBASE,	/* mii base */
+	 CONFIG_SYS_FEC1_IOBASE,	/* io base */
+	 CONFIG_SYS_FEC1_PINMUX,	/* gpio pin muxing */
+	 CONFIG_SYS_FEC1_MIIBASE,	/* mii base */
 	 -1,			/* phy_addr */
 	 0,			/* duplex and speed */
 	 0,			/* phy name */
 	 0,			/* phy name init */
-#ifdef CFG_FEC_BUF_USE_SRAM
+#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
 	 (cbd_t *)DBUF_LENGTH,	/* RX BD */
 #else
 	 0,			/* RX BD */
@@ -100,18 +101,6 @@ int fec_init(struct eth_device *dev, bd_t * bd);
 void fec_halt(struct eth_device *dev);
 void fec_reset(struct eth_device *dev);
 
-extern int fecpin_setclear(struct eth_device *dev, int setclear);
-
-#ifdef CFG_DISCOVER_PHY
-extern void __mii_init(void);
-extern uint mii_send(uint mii_cmd);
-extern int mii_discover_phy(struct eth_device *dev);
-extern int mcffec_miiphy_read(char *devname, unsigned char addr,
-			      unsigned char reg, unsigned short *value);
-extern int mcffec_miiphy_write(char *devname, unsigned char addr,
-			       unsigned char reg, unsigned short value);
-#endif
-
 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
 {
 	if ((dup_spd >> 16) == FULL) {
@@ -174,7 +163,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
 	/* Activate transmit Buffer Descriptor polling */
 	fecp->tdar = 0x01000000;	/* Descriptor polling active    */
 
-#ifndef CFG_FEC_BUF_USE_SRAM
+#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
 	/*
 	 * FEC unable to initial transmit data packet.
 	 * A nop will ensure the descriptor polling active completed.
@@ -186,7 +175,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
 
 #endif
 
-#ifdef CFG_UNIFY_CACHE
+#ifdef CONFIG_SYS_UNIFY_CACHE
 	icache_invalid();
 #endif
 
@@ -221,9 +210,9 @@ int fec_recv(struct eth_device *dev)
 	int length;
 
 	for (;;) {
-#ifndef CFG_FEC_BUF_USE_SRAM
+#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
 #endif
-#ifdef CFG_UNIFY_CACHE
+#ifdef CONFIG_SYS_UNIFY_CACHE
 		icache_invalid();
 #endif
 		/* section 16.9.23.2 */
@@ -434,15 +423,15 @@ int fec_init(struct eth_device *dev, bd_t * bd)
 	fec_reset(dev);
 
 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
-	defined (CFG_DISCOVER_PHY)
+	defined (CONFIG_SYS_DISCOVER_PHY)
 
 	mii_init();
 
 	setFecDuplexSpeed(fecp, bd, info->dup_spd);
 #else
-#ifndef CFG_DISCOVER_PHY
+#ifndef CONFIG_SYS_DISCOVER_PHY
 	setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
-#endif				/* ifndef CFG_DISCOVER_PHY */
+#endif				/* ifndef CONFIG_SYS_DISCOVER_PHY */
 #endif				/* CONFIG_CMD_MII || CONFIG_MII */
 
 	/* We use strictly polling mode only */
@@ -452,9 +441,9 @@ int fec_init(struct eth_device *dev, bd_t * bd)
 	fecp->eir = 0xffffffff;
 
 	/* Set station address   */
-	if ((u32) fecp == CFG_FEC0_IOBASE) {
-#ifdef CFG_FEC1_IOBASE
-		volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE);
+	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
+#ifdef CONFIG_SYS_FEC1_IOBASE
+		volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
 		ea = &bd->bi_enet1addr[0];
 		fecp1->palr =
 		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
@@ -465,14 +454,14 @@ int fec_init(struct eth_device *dev, bd_t * bd)
 		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
 		fecp->paur = (ea[4] << 24) | (ea[5] << 16);
 	} else {
-#ifdef CFG_FEC0_IOBASE
-		volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE);
+#ifdef CONFIG_SYS_FEC0_IOBASE
+		volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
 		ea = &bd->bi_enetaddr[0];
 		fecp0->palr =
 		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
 		fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
 #endif
-#ifdef CFG_FEC1_IOBASE
+#ifdef CONFIG_SYS_FEC1_IOBASE
 		ea = &bd->bi_enet1addr[0];
 		fecp->palr =
 		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
@@ -567,14 +556,14 @@ int mcffec_initialize(bd_t * bis)
 {
 	struct eth_device *dev;
 	int i;
-#ifdef CFG_FEC_BUF_USE_SRAM
-	u32 tmp = CFG_INIT_RAM_ADDR + 0x1000;
+#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+	u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
 #endif
 
 	for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
 
 		dev =
-		    (struct eth_device *)memalign(CFG_CACHELINE_SIZE,
+		    (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
 						  sizeof *dev);
 		if (dev == NULL)
 			hang();
@@ -590,7 +579,7 @@ int mcffec_initialize(bd_t * bis)
 		dev->recv = fec_recv;
 
 		/* setup Receive and Transmit buffer descriptor */
-#ifdef CFG_FEC_BUF_USE_SRAM
+#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
 		fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
 		tmp = (u32)fec_info[i].rxbd;
 		fec_info[i].txbd =
@@ -599,17 +588,17 @@ int mcffec_initialize(bd_t * bis)
 		tmp = (u32)fec_info[i].txbd;
 		fec_info[i].txbuf =
 		    (char *)((u32)fec_info[i].txbuf + tmp +
-		    (CFG_TX_ETH_BUFFER * sizeof(cbd_t)));
+		    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
 		tmp = (u32)fec_info[i].txbuf;
 #else
 		fec_info[i].rxbd =
-		    (cbd_t *) memalign(CFG_CACHELINE_SIZE,
+		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
 				       (PKTBUFSRX * sizeof(cbd_t)));
 		fec_info[i].txbd =
-		    (cbd_t *) memalign(CFG_CACHELINE_SIZE,
+		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
 				       (TX_BUF_CNT * sizeof(cbd_t)));
 		fec_info[i].txbuf =
-		    (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
+		    (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
 #endif
 
 #ifdef ET_DEBUG
@@ -617,7 +606,7 @@ int mcffec_initialize(bd_t * bis)
 		       (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
 #endif
 
-		fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
+		fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
 
 		eth_register(dev);
 
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
new file mode 100644
index 0000000..2b733c6
--- /dev/null
+++ b/drivers/net/mcfmii.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+#include <netdev.h>
+
+#ifdef CONFIG_MCF547x_8x
+#include <asm/fsl_mcdmafec.h>
+#else
+#include <asm/fec.h>
+#endif
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+/*extern int fecpin_setclear(struct eth_device *dev, int setclear);*/
+
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG)		(0x60020000 | ((ADDR << 23) | \
+					 (REG & 0x1f) << 18))
+#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | \
+					 (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+#ifndef CONFIG_SYS_UNSPEC_PHYID
+#	define CONFIG_SYS_UNSPEC_PHYID		0
+#endif
+#ifndef CONFIG_SYS_UNSPEC_STRID
+#	define CONFIG_SYS_UNSPEC_STRID		0
+#endif
+
+#ifdef CONFIG_MCF547x_8x
+typedef struct fec_info_dma FEC_INFO_T;
+#define FEC_T fecdma_t
+#else
+typedef struct fec_info_s FEC_INFO_T;
+#define FEC_T fec_t
+#endif
+
+typedef struct phy_info_struct {
+	u32 phyid;
+	char *strid;
+} phy_info_t;
+
+phy_info_t phyinfo[] = {
+	{0x0022561B, "AMD79C784VC"},	/* AMD 79C784VC */
+	{0x00406322, "BCM5222"},	/* Broadcom 5222 */
+	{0x02a80150, "Intel82555"},	/* Intel 82555 */
+	{0x0016f870, "LSI80225"},	/* LSI 80225 */
+	{0x0016f880, "LSI80225/B"},	/* LSI 80225/B */
+	{0x78100000, "LXT970"},		/* LXT970 */
+	{0x001378e0, "LXT971"},		/* LXT971 and 972 */
+	{0x00221619, "KS8721BL"},	/* Micrel KS8721BL/SL */
+	{0x00221512, "KSZ8041NL"},	/* Micrel KSZ8041NL */
+	{0x20005CE1, "N83640"},		/* National 83640 */
+	{0x20005C90, "N83848"},		/* National 83848 */
+	{0x20005CA2, "N83849"},		/* National 83849 */
+	{0x01814400, "QS6612"},		/* QS6612 */
+#if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID)
+	{CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID},
+#endif
+	{0, 0}
+};
+
+/*
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ */
+void mii_reset(FEC_INFO_T *info)
+{
+	volatile FEC_T *fecp = (FEC_T *) (info->miibase);
+	int i;
+
+	fecp->ecr = FEC_ECR_RESET;
+
+	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+		udelay(1);
+	}
+	if (i == FEC_RESET_DELAY)
+		printf("FEC_RESET_DELAY timeout\n");
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+	FEC_INFO_T *info;
+	volatile FEC_T *ep;
+	struct eth_device *dev;
+	uint mii_reply;
+	int j = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	ep = (FEC_T *) info->miibase;
+
+	ep->mmfr = mii_cmd;	/* command to phy */
+
+	/* wait for mii complete */
+	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+		udelay(1);
+		j++;
+	}
+	if (j >= MCFFEC_TOUT_LOOP) {
+		printf("MII not complete\n");
+		return -1;
+	}
+
+	mii_reply = ep->mmfr;	/* result from phy */
+	ep->eir = FEC_EIR_MII;	/* clear MII complete */
+#ifdef ET_DEBUG
+	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+	return (mii_reply & 0xffff);	/* data read from phy */
+}
+#endif				/* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
+
+#if defined(CONFIG_SYS_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+	FEC_INFO_T *info = dev->priv;
+	int phyaddr, pass;
+	uint phyno, phytype;
+	int i, found = 0;
+
+	if (info->phyname_init)
+		return info->phy_addr;
+
+	phyaddr = -1;		/* didn't find a PHY yet */
+	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+		if (pass > 1) {
+			/* PHY may need more time to recover from reset.
+			 * The LXT970 needs 50ms typical, no maximum is
+			 * specified, so wait 10ms before try again.
+			 * With 11 passes this gives it 100ms to wake up.
+			 */
+			udelay(10000);	/* wait 10ms */
+		}
+
+		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+			printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+			if (phytype != 0xffff) {
+				phyaddr = phyno;
+				phytype <<= 16;
+				phytype |=
+				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+#ifdef ET_DEBUG
+				printf("PHY @ 0x%x pass %d\n", phyno, pass);
+#endif
+
+				for (i = 0; i < (sizeof(phyinfo) / sizeof(phy_info_t)); i++) {
+					if (phyinfo[i].phyid == phytype) {
+#ifdef ET_DEBUG
+						printf("phyid %x - %s\n",
+						       phyinfo[i].phyid,
+						       phyinfo[i].strid);
+#endif
+						strcpy(info->phy_name, phyinfo[i].strid);
+						info->phyname_init = 1;
+						found = 1;
+						break;
+					}
+				}
+
+				if (!found) {
+#ifdef ET_DEBUG
+					printf("0x%08x\n", phytype);
+#endif
+					strcpy(info->phy_name, "unknown");
+					info->phyname_init = 1;
+					break;
+				}
+			}
+		}
+	}
+
+	if (phyaddr < 0)
+		printf("No PHY device found.\n");
+
+	return phyaddr;
+}
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
+
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+	FEC_INFO_T *info;
+	volatile FEC_T *fecp;
+	struct eth_device *dev;
+	int miispd = 0, i = 0;
+	u16 autoneg = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	fecp = (FEC_T *) info->miibase;
+
+	fecpin_setclear(dev, 1);
+
+	mii_reset(info);
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	/* Set MII speed */
+	miispd = (gd->bus_clk / 1000000) / 5;
+	fecp->mscr = miispd << 1;
+
+	info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+	while (i < MCFFEC_TOUT_LOOP) {
+		autoneg = 0;
+		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+		i++;
+
+		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+			break;
+
+		udelay(500);
+	}
+	if (i >= MCFFEC_TOUT_LOOP) {
+		printf("Auto Negotiation not complete\n");
+	}
+
+	/* adapt to the half/full speed settings */
+	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ *	  no PHY connected...
+ *	  For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ *	  Otherwise they hang in mii_send() !!! Sorry!
+ */
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+		       unsigned short *value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+	rdreg = mii_send(mk_mii_read(addr, reg));
+
+	*value = rdreg;
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", *value);
+#endif
+
+	return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+			unsigned short value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+	rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", value);
+#endif
+
+	return 0;
+}
+
+#endif				/* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index 7caeeda..7078c4e 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -10,6 +10,7 @@
 #include <mpc512x.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <miiphy.h>
 #include "mpc512x_fec.h"
 
@@ -363,7 +364,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
 			/*
 			 * Wait for AN completion
 			 */
-			timeout = 50000;
+			timeout = 2500;
 			do {
 				udelay (1000);
 
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
index 3d3eb8b..f8618b1 100644
--- a/drivers/net/mpc5xxx_fec.c
+++ b/drivers/net/mpc5xxx_fec.c
@@ -11,6 +11,7 @@
 #include <mpc5xxx_sdma.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <miiphy.h>
 #include "mpc5xxx_fec.h"
 
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index 4aee048..ce12c3b 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -53,6 +53,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 
@@ -408,7 +409,7 @@ natsemi_initialize(bd_t * bis)
    The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses.  */
 
 /* Delay between EEPROM clock transitions.
-   No extra delay is needed with 33Mhz PCI, but future 66Mhz
+   No extra delay is needed with 33MHz PCI, but future 66MHz
    access may need a delay. */
 #define eeprom_delay(ee_addr)	INL(dev, ee_addr)
 
diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c
index ec92485..ab5eec7 100644
--- a/drivers/net/ne2000.c
+++ b/drivers/net/ne2000.c
@@ -74,600 +74,11 @@ Add SNMP
 
 #include <common.h>
 #include <command.h>
-#include <net.h>
-#include <malloc.h>
-
-#define mdelay(n)	udelay((n)*1000)
-/* forward definition of function used for the uboot interface */
-void uboot_push_packet_len(int len);
-void uboot_push_tx_done(int key, int val);
-
-/*
- * Debugging details
- *
- * Set to perms of:
- * 0 disables all debug output
- * 1 for process debug output
- * 2 for added data IO output: get_reg, put_reg
- * 4 for packet allocation/free output
- * 8 for only startup status, so we can tell we're installed OK
- */
-#if 0
-#define DEBUG 0xf
-#else
-#define DEBUG 0
-#endif
-
-#if DEBUG & 1
-#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
-#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
-#define PRINTK(args...) printf(args)
-#else
-#define DEBUG_FUNCTION() do {} while(0)
-#define DEBUG_LINE() do {} while(0)
-#define PRINTK(args...)
-#endif
 
 /* NE2000 base header file */
 #include "ne2000_base.h"
 
-#if defined(CONFIG_DRIVER_AX88796L)
-/* AX88796L support */
-#include "ax88796.h"
-#else
-/* Basic NE2000 chip support */
-#include "ne2000.h"
-#endif
-
-static dp83902a_priv_data_t nic; /* just one instance of the card supported */
-
-static bool
-dp83902a_init(void)
-{
-	dp83902a_priv_data_t *dp = &nic;
-	u8* base;
-#if defined(NE2000_BASIC_INIT)
-	int i;
-#endif
-
-	DEBUG_FUNCTION();
-
-	base = dp->base;
-	if (!base)
-		return false;	/* No device found */
-
-	DEBUG_LINE();
-
-#if defined(NE2000_BASIC_INIT)
-	/* AX88796L doesn't need */
-	/* Prepare ESA */
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);	/* Select page 1 */
-	/* Use the address from the serial EEPROM */
-	for (i = 0; i < 6; i++)
-		DP_IN(base, DP_P1_PAR0+i, dp->esa[i]);
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0);	/* Select page 0 */
-
-	printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
-		"eeprom",
-		dp->esa[0],
-		dp->esa[1],
-		dp->esa[2],
-		dp->esa[3],
-		dp->esa[4],
-		dp->esa[5] );
-
-#endif	/* NE2000_BASIC_INIT */
-	return true;
-}
-
-static void
-dp83902a_stop(void)
-{
-	dp83902a_priv_data_t *dp = &nic;
-	u8 *base = dp->base;
-
-	DEBUG_FUNCTION();
-
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP);	/* Brutal */
-	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
-	DP_OUT(base, DP_IMR, 0x00);		/* Disable all interrupts */
-
-	dp->running = false;
-}
-
-/*
- * This function is called to "start up" the interface. It may be called
- * multiple times, even when the hardware is already running. It will be
- * called whenever something "hardware oriented" changes and should leave
- * the hardware ready to send/receive packets.
- */
-static void
-dp83902a_start(u8 * enaddr)
-{
-	dp83902a_priv_data_t *dp = &nic;
-	u8 *base = dp->base;
-	int i;
-
-	DEBUG_FUNCTION();
-
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
-	DP_OUT(base, DP_DCR, DP_DCR_INIT);
-	DP_OUT(base, DP_RBCH, 0);		/* Remote byte count */
-	DP_OUT(base, DP_RBCL, 0);
-	DP_OUT(base, DP_RCR, DP_RCR_MON);	/* Accept no packets */
-	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);	/* Transmitter [virtually] off */
-	DP_OUT(base, DP_TPSR, dp->tx_buf1);	/* Transmitter start page */
-	dp->tx1 = dp->tx2 = 0;
-	dp->tx_next = dp->tx_buf1;
-	dp->tx_started = false;
-	dp->running = true;
-	DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
-	DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */
-	DP_OUT(base, DP_PSTOP, dp->rx_buf_end);	/* Receive ring end page */
-	dp->rx_next = dp->rx_buf_start - 1;
-	dp->running = true;
-	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
-	DP_OUT(base, DP_IMR, DP_IMR_All);	/* Enable all interrupts */
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP);	/* Select page 1 */
-	DP_OUT(base, DP_P1_CURP, dp->rx_buf_start);	/* Current page - next free page for Rx */
-	dp->running = true;
-	for (i = 0; i < ETHER_ADDR_LEN; i++) {
-		/* FIXME */
-		/*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) +
-		 * 0x1400)) = enaddr[i];*/
-		DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
-	}
-	/* Enable and start device */
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-	DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
-	DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */
-	dp->running = true;
-}
-
-/*
- * This routine is called to start the transmitter. It is split out from the
- * data handling routine so it may be called either when data becomes first
- * available or when an Tx interrupt occurs
- */
-
-static void
-dp83902a_start_xmit(int start_page, int len)
-{
-	dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
-	u8 *base = dp->base;
-
-	DEBUG_FUNCTION();
-
-#if DEBUG & 1
-	printf("Tx pkt %d len %d\n", start_page, len);
-	if (dp->tx_started)
-		printf("TX already started?!?\n");
-#endif
-
-	DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE));
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-	DP_OUT(base, DP_TBCL, len & 0xFF);
-	DP_OUT(base, DP_TBCH, len >> 8);
-	DP_OUT(base, DP_TPSR, start_page);
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
-
-	dp->tx_started = true;
-}
-
-/*
- * This routine is called to send data to the hardware. It is known a-priori
- * that there is free buffer space (dp->tx_next).
- */
-static void
-dp83902a_send(u8 *data, int total_len, u32 key)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	int len, start_page, pkt_len, i, isr;
-#if DEBUG & 4
-	int dx;
-#endif
-
-	DEBUG_FUNCTION();
-
-	len = pkt_len = total_len;
-	if (pkt_len < IEEE_8023_MIN_FRAME)
-		pkt_len = IEEE_8023_MIN_FRAME;
-
-	start_page = dp->tx_next;
-	if (dp->tx_next == dp->tx_buf1) {
-		dp->tx1 = start_page;
-		dp->tx1_len = pkt_len;
-		dp->tx1_key = key;
-		dp->tx_next = dp->tx_buf2;
-	} else {
-		dp->tx2 = start_page;
-		dp->tx2_len = pkt_len;
-		dp->tx2_key = key;
-		dp->tx_next = dp->tx_buf1;
-	}
-
-#if DEBUG & 5
-	printf("TX prep page %d len %d\n", start_page, pkt_len);
-#endif
-
-	DP_OUT(base, DP_ISR, DP_ISR_RDC);	/* Clear end of DMA */
-	{
-		/*
-		 * Dummy read. The manual sez something slightly different,
-		 * but the code is extended a bit to do what Hitachi's monitor
-		 * does (i.e., also read data).
-		 */
-
-		u16 tmp;
-		int len = 1;
-
-		DP_OUT(base, DP_RSAL, 0x100 - len);
-		DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff);
-		DP_OUT(base, DP_RBCL, len);
-		DP_OUT(base, DP_RBCH, 0);
-		DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START);
-		DP_IN_DATA(dp->data, tmp);
-	}
-
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
-	/*
-	 * Stall for a bit before continuing to work around random data
-	 * corruption problems on some platforms.
-	 */
-	CYGACC_CALL_IF_DELAY_US(1);
-#endif
-
-	/* Send data to device buffer(s) */
-	DP_OUT(base, DP_RSAL, 0);
-	DP_OUT(base, DP_RSAH, start_page);
-	DP_OUT(base, DP_RBCL, pkt_len & 0xFF);
-	DP_OUT(base, DP_RBCH, pkt_len >> 8);
-	DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START);
-
-	/* Put data into buffer */
-#if DEBUG & 4
-	printf(" sg buf %08lx len %08x\n ", (u32)data, len);
-	dx = 0;
-#endif
-	while (len > 0) {
-#if DEBUG & 4
-		printf(" %02x", *data);
-		if (0 == (++dx % 16)) printf("\n ");
-#endif
-
-		DP_OUT_DATA(dp->data, *data++);
-		len--;
-	}
-#if DEBUG & 4
-	printf("\n");
-#endif
-	if (total_len < pkt_len) {
-#if DEBUG & 4
-		printf("  + %d bytes of padding\n", pkt_len - total_len);
-#endif
-		/* Padding to 802.3 length was required */
-		for (i = total_len; i < pkt_len;) {
-			i++;
-			DP_OUT_DATA(dp->data, 0);
-		}
-	}
-
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
-	/*
-	 * After last data write, delay for a bit before accessing the
-	 * device again, or we may get random data corruption in the last
-	 * datum (on some platforms).
-	 */
-	CYGACC_CALL_IF_DELAY_US(1);
-#endif
-
-	/* Wait for DMA to complete */
-	do {
-		DP_IN(base, DP_ISR, isr);
-	} while ((isr & DP_ISR_RDC) == 0);
-
-	/* Then disable DMA */
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-
-	/* Start transmit if not already going */
-	if (!dp->tx_started) {
-		if (start_page == dp->tx1) {
-			dp->tx_int = 1; /* Expecting interrupt from BUF1 */
-		} else {
-			dp->tx_int = 2; /* Expecting interrupt from BUF2 */
-		}
-		dp83902a_start_xmit(start_page, pkt_len);
-	}
-}
-
-/*
- * This function is called when a packet has been received. It's job is
- * to prepare to unload the packet from the hardware. Once the length of
- * the packet is known, the upper layer of the driver can be told. When
- * the upper layer is ready to unload the packet, the internal function
- * 'dp83902a_recv' will be called to actually fetch it from the hardware.
- */
-static void
-dp83902a_RxEvent(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	u8 rsr;
-	u8 rcv_hdr[4];
-	int i, len, pkt, cur;
-
-	DEBUG_FUNCTION();
-
-	DP_IN(base, DP_RSR, rsr);
-	while (true) {
-		/* Read incoming packet header */
-		DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START);
-		DP_IN(base, DP_P1_CURP, cur);
-		DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-		DP_IN(base, DP_BNDRY, pkt);
-
-		pkt += 1;
-		if (pkt == dp->rx_buf_end)
-			pkt = dp->rx_buf_start;
-
-		if (pkt == cur) {
-			break;
-		}
-		DP_OUT(base, DP_RBCL, sizeof(rcv_hdr));
-		DP_OUT(base, DP_RBCH, 0);
-		DP_OUT(base, DP_RSAL, 0);
-		DP_OUT(base, DP_RSAH, pkt);
-		if (dp->rx_next == pkt) {
-			if (cur == dp->rx_buf_start)
-				DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
-			else
-				DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */
-			return;
-		}
-		dp->rx_next = pkt;
-		DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
-		DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
-		CYGACC_CALL_IF_DELAY_US(10);
-#endif
-
-		/* read header (get data size)*/
-		for (i = 0; i < sizeof(rcv_hdr);) {
-			DP_IN_DATA(dp->data, rcv_hdr[i++]);
-		}
-
-#if DEBUG & 5
-		printf("rx hdr %02x %02x %02x %02x\n",
-			rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
-#endif
-		len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
-
-		/* data read */
-		uboot_push_packet_len(len);
-
-		if (rcv_hdr[1] == dp->rx_buf_start)
-			DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
-		else
-			DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */
-	}
-}
-
-/*
- * This function is called as a result of the "eth_drv_recv()" call above.
- * It's job is to actually fetch data for a packet from the hardware once
- * memory buffers have been allocated for the packet. Note that the buffers
- * may come in pieces, using a scatter-gather list. This allows for more
- * efficient processing in the upper layers of the stack.
- */
-static void
-dp83902a_recv(u8 *data, int len)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	int i, mlen;
-	u8 saved_char = 0;
-	bool saved;
-#if DEBUG & 4
-	int dx;
-#endif
-
-	DEBUG_FUNCTION();
-
-#if DEBUG & 5
-	printf("Rx packet %d length %d\n", dp->rx_next, len);
-#endif
-
-	/* Read incoming packet data */
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-	DP_OUT(base, DP_RBCL, len & 0xFF);
-	DP_OUT(base, DP_RBCH, len >> 8);
-	DP_OUT(base, DP_RSAL, 4);		/* Past header */
-	DP_OUT(base, DP_RSAH, dp->rx_next);
-	DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
-	DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
-	CYGACC_CALL_IF_DELAY_US(10);
-#endif
-
-	saved = false;
-	for (i = 0; i < 1; i++) {
-		if (data) {
-			mlen = len;
-#if DEBUG & 4
-			printf(" sg buf %08lx len %08x \n", (u32) data, mlen);
-			dx = 0;
-#endif
-			while (0 < mlen) {
-				/* Saved byte from previous loop? */
-				if (saved) {
-					*data++ = saved_char;
-					mlen--;
-					saved = false;
-					continue;
-				}
-
-				{
-					u8 tmp;
-					DP_IN_DATA(dp->data, tmp);
-#if DEBUG & 4
-					printf(" %02x", tmp);
-					if (0 == (++dx % 16)) printf("\n ");
-#endif
-					*data++ = tmp;;
-					mlen--;
-				}
-			}
-#if DEBUG & 4
-			printf("\n");
-#endif
-		}
-	}
-}
-
-static void
-dp83902a_TxEvent(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	u8 tsr;
-	u32 key;
-
-	DEBUG_FUNCTION();
-
-	DP_IN(base, DP_TSR, tsr);
-	if (dp->tx_int == 1) {
-		key = dp->tx1_key;
-		dp->tx1 = 0;
-	} else {
-		key = dp->tx2_key;
-		dp->tx2 = 0;
-	}
-	/* Start next packet if one is ready */
-	dp->tx_started = false;
-	if (dp->tx1) {
-		dp83902a_start_xmit(dp->tx1, dp->tx1_len);
-		dp->tx_int = 1;
-	} else if (dp->tx2) {
-		dp83902a_start_xmit(dp->tx2, dp->tx2_len);
-		dp->tx_int = 2;
-	} else {
-		dp->tx_int = 0;
-	}
-	/* Tell higher level we sent this packet */
-	uboot_push_tx_done(key, 0);
-}
-
-/*
- * Read the tally counters to clear them. Called in response to a CNT
- * interrupt.
- */
-static void
-dp83902a_ClearCounters(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	u8 cnt1, cnt2, cnt3;
-
-	DP_IN(base, DP_FER, cnt1);
-	DP_IN(base, DP_CER, cnt2);
-	DP_IN(base, DP_MISSED, cnt3);
-	DP_OUT(base, DP_ISR, DP_ISR_CNT);
-}
-
-/*
- * Deal with an overflow condition. This code follows the procedure set
- * out in section 7.0 of the datasheet.
- */
-static void
-dp83902a_Overflow(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
-	u8 *base = dp->base;
-	u8 isr;
-
-	/* Issue a stop command and wait 1.6ms for it to complete. */
-	DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
-	CYGACC_CALL_IF_DELAY_US(1600);
-
-	/* Clear the remote byte counter registers. */
-	DP_OUT(base, DP_RBCL, 0);
-	DP_OUT(base, DP_RBCH, 0);
-
-	/* Enter loopback mode while we clear the buffer. */
-	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);
-	DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA);
-
-	/*
-	 * Read in as many packets as we can and acknowledge any and receive
-	 * interrupts. Since the buffer has overflowed, a receive event of
-	 * some kind will have occured.
-	 */
-	dp83902a_RxEvent();
-	DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
-
-	/* Clear the overflow condition and leave loopback mode. */
-	DP_OUT(base, DP_ISR, DP_ISR_OFLW);
-	DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
-
-	/*
-	 * If a transmit command was issued, but no transmit event has occured,
-	 * restart it here.
-	 */
-	DP_IN(base, DP_ISR, isr);
-	if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) {
-		DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
-	}
-}
-
-static void
-dp83902a_poll(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	u8 isr;
-
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
-	DP_IN(base, DP_ISR, isr);
-	while (0 != isr) {
-		/*
-		 * The CNT interrupt triggers when the MSB of one of the error
-		 * counters is set. We don't much care about these counters, but
-		 * we should read their values to reset them.
-		 */
-		if (isr & DP_ISR_CNT) {
-			dp83902a_ClearCounters();
-		}
-		/*
-		 * Check for overflow. It's a special case, since there's a
-		 * particular procedure that must be followed to get back into
-		 * a running state.a
-		 */
-		if (isr & DP_ISR_OFLW) {
-			dp83902a_Overflow();
-		} else {
-			/*
-			 * Other kinds of interrupts can be acknowledged simply by
-			 * clearing the relevant bits of the ISR. Do that now, then
-			 * handle the interrupts we care about.
-			 */
-			DP_OUT(base, DP_ISR, isr);	/* Clear set bits */
-			if (!dp->running) break;	/* Is this necessary? */
-			/*
-			 * Check for tx_started on TX event since these may happen
-			 * spuriously it seems.
-			 */
-			if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) {
-				dp83902a_TxEvent();
-			}
-			if (isr & (DP_ISR_RxP|DP_ISR_RxE)) {
-				dp83902a_RxEvent();
-			}
-		}
-		DP_IN(base, DP_ISR, isr);
-	}
-}
-
+#define mdelay(n) udelay((n)*1000)
 /* find prom (taken from pc_net_cs.c from Linux) */
 
 #include "8390.h"
@@ -763,18 +174,16 @@ static hw_info_t hw_info[] = {
 #define PCNET_RESET	0x1f	/* Issue a read to reset, a write to clear. */
 #define PCNET_MISC	0x18	/* For IBM CCAE and Socket EA cards */
 
-static void pcnet_reset_8390(void)
+static void pcnet_reset_8390(u8* addr)
 {
 	int i, r;
 
-	PRINTK("nic base is %lx\n", nic.base);
-
 	n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD));
+	PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
 	n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD));
+	PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
 	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD));
+	PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
 	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
 
 	n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
@@ -791,8 +200,7 @@ static void pcnet_reset_8390(void)
 		printf("pcnet_reset_8390() did not complete.\n");
 } /* pcnet_reset_8390 */
 
-int get_prom(u8* mac_addr) __attribute__ ((weak, alias ("__get_prom")));
-int __get_prom(u8* mac_addr)
+int get_prom(u8* mac_addr, u8* base_addr)
 {
 	u8 prom[32];
 	int i, j;
@@ -816,7 +224,7 @@ int __get_prom(u8* mac_addr)
 
 	PRINTK ("trying to get MAC via prom reading\n");
 
-	pcnet_reset_8390 ();
+	pcnet_reset_8390 (base_addr);
 
 	mdelay (10);
 
@@ -849,116 +257,3 @@ int __get_prom(u8* mac_addr)
 	}
 	return 0;
 }
-
-/* U-boot specific routines */
-static u8 *pbuf = NULL;
-
-static int pkey = -1;
-static int initialized = 0;
-
-void uboot_push_packet_len(int len) {
-	PRINTK("pushed len = %d\n", len);
-	if (len >= 2000) {
-		printf("NE2000: packet too big\n");
-		return;
-	}
-	dp83902a_recv(&pbuf[0], len);
-
-	/*Just pass it to the upper layer*/
-	NetReceive(&pbuf[0], len);
-}
-
-void uboot_push_tx_done(int key, int val) {
-	PRINTK("pushed key = %d\n", key);
-	pkey = key;
-}
-
-int eth_init(bd_t *bd) {
-	int r;
-	u8 dev_addr[6];
-	char ethaddr[20];
-
-	PRINTK("### eth_init\n");
-
-	if (!pbuf) {
-		pbuf = malloc(2000);
-		if (!pbuf) {
-			printf("Cannot allocate rx buffer\n");
-			return -1;
-		}
-	}
-
-#ifdef CONFIG_DRIVER_NE2000_CCR
-	{
-		vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
-
-		PRINTK("CCR before is %x\n", *p);
-		*p = CONFIG_DRIVER_NE2000_VAL;
-		PRINTK("CCR after is %x\n", *p);
-	}
-#endif
-
-	nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
-
-	r = get_prom(dev_addr);
-	if (!r)
-		return -1;
-
-	sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-		 dev_addr[0], dev_addr[1],
-		 dev_addr[2], dev_addr[3],
-		 dev_addr[4], dev_addr[5]) ;
-	PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr);
-	setenv ("ethaddr", ethaddr);
-
-	nic.data = nic.base + DP_DATA;
-	nic.tx_buf1 = START_PG;
-	nic.tx_buf2 = START_PG2;
-	nic.rx_buf_start = RX_START;
-	nic.rx_buf_end = RX_END;
-
-	if (dp83902a_init() == false)
-		return -1;
-
-	dp83902a_start(dev_addr);
-	initialized = 1;
-
-	return 0;
-}
-
-void eth_halt() {
-
-	PRINTK("### eth_halt\n");
-	if(initialized)
-		dp83902a_stop();
-	initialized = 0;
-}
-
-int eth_rx() {
-	dp83902a_poll();
-	return 1;
-}
-
-int eth_send(volatile void *packet, int length) {
-	int tmo;
-
-	PRINTK("### eth_send\n");
-
-	pkey = -1;
-
-	dp83902a_send((u8 *) packet, length, 666);
-	tmo = get_timer (0) + TOUT * CFG_HZ;
-	while(1) {
-		dp83902a_poll();
-		if (pkey != -1) {
-			PRINTK("Packet sucesfully sent\n");
-			return 0;
-		}
-		if (get_timer (0) >= tmo) {
-			printf("transmission error (timoeut)\n");
-			return 0;
-		}
-
-	}
-	return 0;
-}
diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c
new file mode 100644
index 0000000..f93f932
--- /dev/null
+++ b/drivers/net/ne2000_base.c
@@ -0,0 +1,757 @@
+/*
+Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
+
+Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
+eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
+are GPL, so this is, of course, GPL.
+
+==========================================================================
+
+dev/if_dp83902a.c
+
+Ethernet device driver for NS DP83902a ethernet controller
+
+==========================================================================
+####ECOSGPLCOPYRIGHTBEGIN####
+-------------------------------------------
+This file is part of eCos, the Embedded Configurable Operating System.
+Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+
+eCos is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2 or (at your option) any later version.
+
+eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License along
+with eCos; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+As a special exception, if other files instantiate templates or use macros
+or inline functions from this file, or you compile this file and link it
+with other works to produce a work based on this file, this file does not
+by itself cause the resulting work to be covered by the GNU General Public
+License. However the source code for this file must still be made available
+in accordance with section (3) of the GNU General Public License.
+
+This exception does not invalidate any other reasons why a work based on
+this file might be covered by the GNU General Public License.
+
+Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+at http://sources.redhat.com/ecos/ecos-license/
+-------------------------------------------
+####ECOSGPLCOPYRIGHTEND####
+####BSDCOPYRIGHTBEGIN####
+
+-------------------------------------------
+
+Portions of this software may have been derived from OpenBSD or other sources,
+and are covered by the appropriate copyright disclaimers included herein.
+
+-------------------------------------------
+
+####BSDCOPYRIGHTEND####
+==========================================================================
+#####DESCRIPTIONBEGIN####
+
+Author(s):	gthomas
+Contributors:	gthomas, jskov, rsandifo
+Date:		2001-06-13
+Purpose:
+Description:
+
+FIXME:		Will fail if pinged with large packets (1520 bytes)
+Add promisc config
+Add SNMP
+
+####DESCRIPTIONEND####
+
+==========================================================================
+*/
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+
+#define mdelay(n)	udelay((n)*1000)
+/* forward definition of function used for the uboot interface */
+void uboot_push_packet_len(int len);
+void uboot_push_tx_done(int key, int val);
+
+/* NE2000 base header file */
+#include "ne2000_base.h"
+
+#if defined(CONFIG_DRIVER_AX88796L)
+/* AX88796L support */
+#include "ax88796.h"
+#else
+/* Basic NE2000 chip support */
+#include "ne2000.h"
+#endif
+
+static dp83902a_priv_data_t nic; /* just one instance of the card supported */
+
+static bool
+dp83902a_init(void)
+{
+	dp83902a_priv_data_t *dp = &nic;
+	u8* base;
+#if defined(NE2000_BASIC_INIT)
+	int i;
+#endif
+
+	DEBUG_FUNCTION();
+
+	base = dp->base;
+	if (!base)
+		return false;	/* No device found */
+
+	DEBUG_LINE();
+
+#if defined(NE2000_BASIC_INIT)
+	/* AX88796L doesn't need */
+	/* Prepare ESA */
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);	/* Select page 1 */
+	/* Use the address from the serial EEPROM */
+	for (i = 0; i < 6; i++)
+		DP_IN(base, DP_P1_PAR0+i, dp->esa[i]);
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0);	/* Select page 0 */
+
+	printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
+		"eeprom",
+		dp->esa[0],
+		dp->esa[1],
+		dp->esa[2],
+		dp->esa[3],
+		dp->esa[4],
+		dp->esa[5] );
+
+#endif	/* NE2000_BASIC_INIT */
+	return true;
+}
+
+static void
+dp83902a_stop(void)
+{
+	dp83902a_priv_data_t *dp = &nic;
+	u8 *base = dp->base;
+
+	DEBUG_FUNCTION();
+
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP);	/* Brutal */
+	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
+	DP_OUT(base, DP_IMR, 0x00);		/* Disable all interrupts */
+
+	dp->running = false;
+}
+
+/*
+ * This function is called to "start up" the interface. It may be called
+ * multiple times, even when the hardware is already running. It will be
+ * called whenever something "hardware oriented" changes and should leave
+ * the hardware ready to send/receive packets.
+ */
+static void
+dp83902a_start(u8 * enaddr)
+{
+	dp83902a_priv_data_t *dp = &nic;
+	u8 *base = dp->base;
+	int i;
+
+	DEBUG_FUNCTION();
+
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
+	DP_OUT(base, DP_DCR, DP_DCR_INIT);
+	DP_OUT(base, DP_RBCH, 0);		/* Remote byte count */
+	DP_OUT(base, DP_RBCL, 0);
+	DP_OUT(base, DP_RCR, DP_RCR_MON);	/* Accept no packets */
+	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);	/* Transmitter [virtually] off */
+	DP_OUT(base, DP_TPSR, dp->tx_buf1);	/* Transmitter start page */
+	dp->tx1 = dp->tx2 = 0;
+	dp->tx_next = dp->tx_buf1;
+	dp->tx_started = false;
+	dp->running = true;
+	DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
+	DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */
+	DP_OUT(base, DP_PSTOP, dp->rx_buf_end);	/* Receive ring end page */
+	dp->rx_next = dp->rx_buf_start - 1;
+	dp->running = true;
+	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
+	DP_OUT(base, DP_IMR, DP_IMR_All);	/* Enable all interrupts */
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP);	/* Select page 1 */
+	DP_OUT(base, DP_P1_CURP, dp->rx_buf_start);	/* Current page - next free page for Rx */
+	dp->running = true;
+	for (i = 0; i < ETHER_ADDR_LEN; i++) {
+		/* FIXME */
+		/*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) +
+		 * 0x1400)) = enaddr[i];*/
+		DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
+	}
+	/* Enable and start device */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+	DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
+	DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */
+	dp->running = true;
+}
+
+/*
+ * This routine is called to start the transmitter. It is split out from the
+ * data handling routine so it may be called either when data becomes first
+ * available or when an Tx interrupt occurs
+ */
+
+static void
+dp83902a_start_xmit(int start_page, int len)
+{
+	dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
+	u8 *base = dp->base;
+
+	DEBUG_FUNCTION();
+
+#if DEBUG & 1
+	printf("Tx pkt %d len %d\n", start_page, len);
+	if (dp->tx_started)
+		printf("TX already started?!?\n");
+#endif
+
+	DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE));
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+	DP_OUT(base, DP_TBCL, len & 0xFF);
+	DP_OUT(base, DP_TBCH, len >> 8);
+	DP_OUT(base, DP_TPSR, start_page);
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
+
+	dp->tx_started = true;
+}
+
+/*
+ * This routine is called to send data to the hardware. It is known a-priori
+ * that there is free buffer space (dp->tx_next).
+ */
+static void
+dp83902a_send(u8 *data, int total_len, u32 key)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	int len, start_page, pkt_len, i, isr;
+#if DEBUG & 4
+	int dx;
+#endif
+
+	DEBUG_FUNCTION();
+
+	len = pkt_len = total_len;
+	if (pkt_len < IEEE_8023_MIN_FRAME)
+		pkt_len = IEEE_8023_MIN_FRAME;
+
+	start_page = dp->tx_next;
+	if (dp->tx_next == dp->tx_buf1) {
+		dp->tx1 = start_page;
+		dp->tx1_len = pkt_len;
+		dp->tx1_key = key;
+		dp->tx_next = dp->tx_buf2;
+	} else {
+		dp->tx2 = start_page;
+		dp->tx2_len = pkt_len;
+		dp->tx2_key = key;
+		dp->tx_next = dp->tx_buf1;
+	}
+
+#if DEBUG & 5
+	printf("TX prep page %d len %d\n", start_page, pkt_len);
+#endif
+
+	DP_OUT(base, DP_ISR, DP_ISR_RDC);	/* Clear end of DMA */
+	{
+		/*
+		 * Dummy read. The manual sez something slightly different,
+		 * but the code is extended a bit to do what Hitachi's monitor
+		 * does (i.e., also read data).
+		 */
+
+		u16 tmp;
+		int len = 1;
+
+		DP_OUT(base, DP_RSAL, 0x100 - len);
+		DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff);
+		DP_OUT(base, DP_RBCL, len);
+		DP_OUT(base, DP_RBCH, 0);
+		DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START);
+		DP_IN_DATA(dp->data, tmp);
+	}
+
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
+	/*
+	 * Stall for a bit before continuing to work around random data
+	 * corruption problems on some platforms.
+	 */
+	CYGACC_CALL_IF_DELAY_US(1);
+#endif
+
+	/* Send data to device buffer(s) */
+	DP_OUT(base, DP_RSAL, 0);
+	DP_OUT(base, DP_RSAH, start_page);
+	DP_OUT(base, DP_RBCL, pkt_len & 0xFF);
+	DP_OUT(base, DP_RBCH, pkt_len >> 8);
+	DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START);
+
+	/* Put data into buffer */
+#if DEBUG & 4
+	printf(" sg buf %08lx len %08x\n ", (u32)data, len);
+	dx = 0;
+#endif
+	while (len > 0) {
+#if DEBUG & 4
+		printf(" %02x", *data);
+		if (0 == (++dx % 16)) printf("\n ");
+#endif
+
+		DP_OUT_DATA(dp->data, *data++);
+		len--;
+	}
+#if DEBUG & 4
+	printf("\n");
+#endif
+	if (total_len < pkt_len) {
+#if DEBUG & 4
+		printf("  + %d bytes of padding\n", pkt_len - total_len);
+#endif
+		/* Padding to 802.3 length was required */
+		for (i = total_len; i < pkt_len;) {
+			i++;
+			DP_OUT_DATA(dp->data, 0);
+		}
+	}
+
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
+	/*
+	 * After last data write, delay for a bit before accessing the
+	 * device again, or we may get random data corruption in the last
+	 * datum (on some platforms).
+	 */
+	CYGACC_CALL_IF_DELAY_US(1);
+#endif
+
+	/* Wait for DMA to complete */
+	do {
+		DP_IN(base, DP_ISR, isr);
+	} while ((isr & DP_ISR_RDC) == 0);
+
+	/* Then disable DMA */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+
+	/* Start transmit if not already going */
+	if (!dp->tx_started) {
+		if (start_page == dp->tx1) {
+			dp->tx_int = 1; /* Expecting interrupt from BUF1 */
+		} else {
+			dp->tx_int = 2; /* Expecting interrupt from BUF2 */
+		}
+		dp83902a_start_xmit(start_page, pkt_len);
+	}
+}
+
+/*
+ * This function is called when a packet has been received. It's job is
+ * to prepare to unload the packet from the hardware. Once the length of
+ * the packet is known, the upper layer of the driver can be told. When
+ * the upper layer is ready to unload the packet, the internal function
+ * 'dp83902a_recv' will be called to actually fetch it from the hardware.
+ */
+static void
+dp83902a_RxEvent(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	u8 rsr;
+	u8 rcv_hdr[4];
+	int i, len, pkt, cur;
+
+	DEBUG_FUNCTION();
+
+	DP_IN(base, DP_RSR, rsr);
+	while (true) {
+		/* Read incoming packet header */
+		DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START);
+		DP_IN(base, DP_P1_CURP, cur);
+		DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+		DP_IN(base, DP_BNDRY, pkt);
+
+		pkt += 1;
+		if (pkt == dp->rx_buf_end)
+			pkt = dp->rx_buf_start;
+
+		if (pkt == cur) {
+			break;
+		}
+		DP_OUT(base, DP_RBCL, sizeof(rcv_hdr));
+		DP_OUT(base, DP_RBCH, 0);
+		DP_OUT(base, DP_RSAL, 0);
+		DP_OUT(base, DP_RSAH, pkt);
+		if (dp->rx_next == pkt) {
+			if (cur == dp->rx_buf_start)
+				DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
+			else
+				DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */
+			return;
+		}
+		dp->rx_next = pkt;
+		DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
+		DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
+		CYGACC_CALL_IF_DELAY_US(10);
+#endif
+
+		/* read header (get data size)*/
+		for (i = 0; i < sizeof(rcv_hdr);) {
+			DP_IN_DATA(dp->data, rcv_hdr[i++]);
+		}
+
+#if DEBUG & 5
+		printf("rx hdr %02x %02x %02x %02x\n",
+			rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
+#endif
+		len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
+
+		/* data read */
+		uboot_push_packet_len(len);
+
+		if (rcv_hdr[1] == dp->rx_buf_start)
+			DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
+		else
+			DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */
+	}
+}
+
+/*
+ * This function is called as a result of the "eth_drv_recv()" call above.
+ * It's job is to actually fetch data for a packet from the hardware once
+ * memory buffers have been allocated for the packet. Note that the buffers
+ * may come in pieces, using a scatter-gather list. This allows for more
+ * efficient processing in the upper layers of the stack.
+ */
+static void
+dp83902a_recv(u8 *data, int len)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	int i, mlen;
+	u8 saved_char = 0;
+	bool saved;
+#if DEBUG & 4
+	int dx;
+#endif
+
+	DEBUG_FUNCTION();
+
+#if DEBUG & 5
+	printf("Rx packet %d length %d\n", dp->rx_next, len);
+#endif
+
+	/* Read incoming packet data */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+	DP_OUT(base, DP_RBCL, len & 0xFF);
+	DP_OUT(base, DP_RBCH, len >> 8);
+	DP_OUT(base, DP_RSAL, 4);		/* Past header */
+	DP_OUT(base, DP_RSAH, dp->rx_next);
+	DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
+	DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
+	CYGACC_CALL_IF_DELAY_US(10);
+#endif
+
+	saved = false;
+	for (i = 0; i < 1; i++) {
+		if (data) {
+			mlen = len;
+#if DEBUG & 4
+			printf(" sg buf %08lx len %08x \n", (u32) data, mlen);
+			dx = 0;
+#endif
+			while (0 < mlen) {
+				/* Saved byte from previous loop? */
+				if (saved) {
+					*data++ = saved_char;
+					mlen--;
+					saved = false;
+					continue;
+				}
+
+				{
+					u8 tmp;
+					DP_IN_DATA(dp->data, tmp);
+#if DEBUG & 4
+					printf(" %02x", tmp);
+					if (0 == (++dx % 16)) printf("\n ");
+#endif
+					*data++ = tmp;;
+					mlen--;
+				}
+			}
+#if DEBUG & 4
+			printf("\n");
+#endif
+		}
+	}
+}
+
+static void
+dp83902a_TxEvent(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	u8 tsr;
+	u32 key;
+
+	DEBUG_FUNCTION();
+
+	DP_IN(base, DP_TSR, tsr);
+	if (dp->tx_int == 1) {
+		key = dp->tx1_key;
+		dp->tx1 = 0;
+	} else {
+		key = dp->tx2_key;
+		dp->tx2 = 0;
+	}
+	/* Start next packet if one is ready */
+	dp->tx_started = false;
+	if (dp->tx1) {
+		dp83902a_start_xmit(dp->tx1, dp->tx1_len);
+		dp->tx_int = 1;
+	} else if (dp->tx2) {
+		dp83902a_start_xmit(dp->tx2, dp->tx2_len);
+		dp->tx_int = 2;
+	} else {
+		dp->tx_int = 0;
+	}
+	/* Tell higher level we sent this packet */
+	uboot_push_tx_done(key, 0);
+}
+
+/*
+ * Read the tally counters to clear them. Called in response to a CNT
+ * interrupt.
+ */
+static void
+dp83902a_ClearCounters(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	u8 cnt1, cnt2, cnt3;
+
+	DP_IN(base, DP_FER, cnt1);
+	DP_IN(base, DP_CER, cnt2);
+	DP_IN(base, DP_MISSED, cnt3);
+	DP_OUT(base, DP_ISR, DP_ISR_CNT);
+}
+
+/*
+ * Deal with an overflow condition. This code follows the procedure set
+ * out in section 7.0 of the datasheet.
+ */
+static void
+dp83902a_Overflow(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
+	u8 *base = dp->base;
+	u8 isr;
+
+	/* Issue a stop command and wait 1.6ms for it to complete. */
+	DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
+	CYGACC_CALL_IF_DELAY_US(1600);
+
+	/* Clear the remote byte counter registers. */
+	DP_OUT(base, DP_RBCL, 0);
+	DP_OUT(base, DP_RBCH, 0);
+
+	/* Enter loopback mode while we clear the buffer. */
+	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);
+	DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA);
+
+	/*
+	 * Read in as many packets as we can and acknowledge any and receive
+	 * interrupts. Since the buffer has overflowed, a receive event of
+	 * some kind will have occured.
+	 */
+	dp83902a_RxEvent();
+	DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
+
+	/* Clear the overflow condition and leave loopback mode. */
+	DP_OUT(base, DP_ISR, DP_ISR_OFLW);
+	DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
+
+	/*
+	 * If a transmit command was issued, but no transmit event has occured,
+	 * restart it here.
+	 */
+	DP_IN(base, DP_ISR, isr);
+	if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) {
+		DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
+	}
+}
+
+static void
+dp83902a_poll(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	u8 isr;
+
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
+	DP_IN(base, DP_ISR, isr);
+	while (0 != isr) {
+		/*
+		 * The CNT interrupt triggers when the MSB of one of the error
+		 * counters is set. We don't much care about these counters, but
+		 * we should read their values to reset them.
+		 */
+		if (isr & DP_ISR_CNT) {
+			dp83902a_ClearCounters();
+		}
+		/*
+		 * Check for overflow. It's a special case, since there's a
+		 * particular procedure that must be followed to get back into
+		 * a running state.a
+		 */
+		if (isr & DP_ISR_OFLW) {
+			dp83902a_Overflow();
+		} else {
+			/*
+			 * Other kinds of interrupts can be acknowledged simply by
+			 * clearing the relevant bits of the ISR. Do that now, then
+			 * handle the interrupts we care about.
+			 */
+			DP_OUT(base, DP_ISR, isr);	/* Clear set bits */
+			if (!dp->running) break;	/* Is this necessary? */
+			/*
+			 * Check for tx_started on TX event since these may happen
+			 * spuriously it seems.
+			 */
+			if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) {
+				dp83902a_TxEvent();
+			}
+			if (isr & (DP_ISR_RxP|DP_ISR_RxE)) {
+				dp83902a_RxEvent();
+			}
+		}
+		DP_IN(base, DP_ISR, isr);
+	}
+}
+
+
+/* U-boot specific routines */
+static u8 *pbuf = NULL;
+
+static int pkey = -1;
+static int initialized = 0;
+
+void uboot_push_packet_len(int len) {
+	PRINTK("pushed len = %d\n", len);
+	if (len >= 2000) {
+		printf("NE2000: packet too big\n");
+		return;
+	}
+	dp83902a_recv(&pbuf[0], len);
+
+	/*Just pass it to the upper layer*/
+	NetReceive(&pbuf[0], len);
+}
+
+void uboot_push_tx_done(int key, int val) {
+	PRINTK("pushed key = %d\n", key);
+	pkey = key;
+}
+
+int eth_init(bd_t *bd) {
+	int r;
+	u8 dev_addr[6];
+	char ethaddr[20];
+
+	PRINTK("### eth_init\n");
+
+	if (!pbuf) {
+		pbuf = malloc(2000);
+		if (!pbuf) {
+			printf("Cannot allocate rx buffer\n");
+			return -1;
+		}
+	}
+
+#ifdef CONFIG_DRIVER_NE2000_CCR
+	{
+		vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
+
+		PRINTK("CCR before is %x\n", *p);
+		*p = CONFIG_DRIVER_NE2000_VAL;
+		PRINTK("CCR after is %x\n", *p);
+	}
+#endif
+
+	nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
+
+	r = get_prom(dev_addr, nic.base);
+	if (!r)
+		return -1;
+
+	sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+		 dev_addr[0], dev_addr[1],
+		 dev_addr[2], dev_addr[3],
+		 dev_addr[4], dev_addr[5]) ;
+	PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr);
+	setenv ("ethaddr", ethaddr);
+
+	nic.data = nic.base + DP_DATA;
+	nic.tx_buf1 = START_PG;
+	nic.tx_buf2 = START_PG2;
+	nic.rx_buf_start = RX_START;
+	nic.rx_buf_end = RX_END;
+
+	if (dp83902a_init() == false)
+		return -1;
+
+	dp83902a_start(dev_addr);
+	initialized = 1;
+
+	return 0;
+}
+
+void eth_halt() {
+
+	PRINTK("### eth_halt\n");
+	if(initialized)
+		dp83902a_stop();
+	initialized = 0;
+}
+
+int eth_rx() {
+	dp83902a_poll();
+	return 1;
+}
+
+int eth_send(volatile void *packet, int length) {
+	int tmo;
+
+	PRINTK("### eth_send\n");
+
+	pkey = -1;
+
+	dp83902a_send((u8 *) packet, length, 666);
+	tmo = get_timer (0) + TOUT * CONFIG_SYS_HZ;
+	while(1) {
+		dp83902a_poll();
+		if (pkey != -1) {
+			PRINTK("Packet sucesfully sent\n");
+			return 0;
+		}
+		if (get_timer (0) >= tmo) {
+			printf("transmission error (timoeut)\n");
+			return 0;
+		}
+
+	}
+	return 0;
+}
diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h
index 948b290..5446de4 100644
--- a/drivers/net/ne2000_base.h
+++ b/drivers/net/ne2000_base.h
@@ -80,10 +80,35 @@ are GPL, so this is, of course, GPL.
 #define __NE2000_BASE_H__
 
 #define bool int
-
 #define false 0
 #define true 1
 
+/*
+ * Debugging details
+ *
+ * Set to perms of:
+ * 0 disables all debug output
+ * 1 for process debug output
+ * 2 for added data IO output: get_reg, put_reg
+ * 4 for packet allocation/free output
+ * 8 for only startup status, so we can tell we're installed OK
+ */
+#if 0
+#define DEBUG 0xf
+#else
+#define DEBUG 0
+#endif
+
+#if DEBUG & 1
+#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
+#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
+#define PRINTK(args...) printf(args)
+#else
+#define DEBUG_FUNCTION() do {} while(0)
+#define DEBUG_LINE() do {} while(0)
+#define PRINTK(args...)
+#endif
+
 /* timeout for tx/rx in s */
 #define TOUT 5
 /* Ether MAC address size */
@@ -119,11 +144,6 @@ typedef struct dp83902a_priv_data {
 	int rx_buf_start, rx_buf_end;
 } dp83902a_priv_data_t;
 
-/*
- * Some forward declarations
- */
-static void dp83902a_poll(void);
-
 /* ------------------------------------------------------------------------ */
 /* Register offsets */
 
@@ -281,4 +301,8 @@ static void dp83902a_poll(void);
 
 #define IEEE_8023_MAX_FRAME	1518	/* Largest possible ethernet frame */
 #define IEEE_8023_MIN_FRAME	64	/* Smallest possible ethernet frame */
+
+/* Functions */
+int get_prom(u8* mac_addr, u8* base_addr);
+
 #endif /* __NE2000_BASE_H__ */
diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c
index c011809..c9e324e 100644
--- a/drivers/net/netarm_eth.c
+++ b/drivers/net/netarm_eth.c
@@ -56,7 +56,7 @@ static void na_mii_write (int reg, int value)
 	int mii_addr;
 
 	/* Select register */
-	mii_addr = CFG_ETH_PHY_ADDR + reg;
+	mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
 	SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
 	/* Write value */
 	SET_EADDR (NETARM_ETH_MII_WRITE, value);
@@ -68,7 +68,7 @@ static unsigned int na_mii_read (int reg)
 	int mii_addr, val;
 
 	/* Select register */
-	mii_addr = CFG_ETH_PHY_ADDR + reg;
+	mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
 	SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
 	/* do one management cycle */
 	SET_EADDR (NETARM_ETH_MII_CMD,
diff --git a/drivers/net/ns7520_eth.c b/drivers/net/ns7520_eth.c
index e19c223..c28726e 100644
--- a/drivers/net/ns7520_eth.c
+++ b/drivers/net/ns7520_eth.c
@@ -86,8 +86,8 @@ static int nDebugLvl = DEBUG_ERROR_CRIT;
 # define ASSERT(expr, func)
 #endif				/* DEBUG */
 
-#define NS7520_MII_NEG_DELAY		(5*CFG_HZ)	/* in s */
-#define TX_TIMEOUT			(5*CFG_HZ)	/* in s */
+#define NS7520_MII_NEG_DELAY		(5*CONFIG_SYS_HZ)	/* in s */
+#define TX_TIMEOUT			(5*CONFIG_SYS_HZ)	/* in s */
 #define RX_STALL_WORKAROUND_CNT 100
 
 static int ns7520_eth_reset(void);
diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c
index bb58438..198f73d 100644
--- a/drivers/net/ns8382x.c
+++ b/drivers/net/ns8382x.c
@@ -53,6 +53,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 
@@ -444,7 +445,7 @@ ns8382x_initialize(bd_t * bis)
 	Read and write MII registers using software-generated serial MDIO
 	protocol.  See the MII specifications or DP83840A data sheet for details.
 
-	The maximum data clock rate is 2.5 Mhz.  To meet minimum timing we
+	The maximum data clock rate is 2.5 MHz.  To meet minimum timing we
 	must flush writes to the PCI bus with a PCI read. */
 #define mdio_delay(mdio_addr) INL(dev, mdio_addr)
 
diff --git a/drivers/net/ns9750_eth.c b/drivers/net/ns9750_eth.c
index cade831..d4901b4 100644
--- a/drivers/net/ns9750_eth.c
+++ b/drivers/net/ns9750_eth.c
@@ -90,8 +90,8 @@ static int nDebugLvl = DEBUG_ERROR_CRIT;
 # define ASSERT(expr, func)
 #endif /* DEBUG */
 
-#define NS9750_MII_NEG_DELAY		(5*CFG_HZ) /* in s */
-#define TX_TIMEOUT			(5*CFG_HZ) /* in s */
+#define NS9750_MII_NEG_DELAY		(5*CONFIG_SYS_HZ) /* in s */
+#define TX_TIMEOUT			(5*CONFIG_SYS_HZ) /* in s */
 
 /* @TODO move it to eeprom.h */
 #define FS_EEPROM_AUTONEG_MASK		0x7
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index a4f0214..99b6942 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -26,6 +26,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index 6446012..e3c163a 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -39,7 +39,7 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
 {
 	int j;			/* counter */
 #if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
-	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+	volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
 #endif
 
 	/*
@@ -124,7 +124,7 @@ int bb_miiphy_read (char *devname, unsigned char addr,
 	short rdreg;		/* register working value */
 	int j;			/* counter */
 #if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
-	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+	volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
 #endif
 
 	miiphy_pre (1, addr, reg);
@@ -191,7 +191,7 @@ int bb_miiphy_write (char *devname, unsigned char addr,
 {
 	int j;			/* counter */
 #if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
-	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+	volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
 #endif
 
 	miiphy_pre (0, addr, reg);
diff --git a/drivers/net/plb2800_eth.c b/drivers/net/plb2800_eth.c
index dad842c..d799c73 100644
--- a/drivers/net/plb2800_eth.c
+++ b/drivers/net/plb2800_eth.c
@@ -26,6 +26,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/addrspace.h>
 
 
@@ -105,7 +106,7 @@ int plb2800_eth_initialize(bd_t * bis)
 	if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
 	{
 		printf("Failed to allocate memory\n");
-		return 0;
+		return -1;
 	}
 	memset(dev, 0, sizeof(*dev));
 
@@ -140,7 +141,7 @@ int plb2800_eth_initialize(bd_t * bis)
 	printf("Leaving plb2800_eth_initialize()\n");
 #endif
 
-	return 1;
+	return 0;
 }
 
 static int plb2800_eth_init(struct eth_device *dev, bd_t * bis)
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index 4fd20ac..db8a727 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -74,6 +74,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 
@@ -286,7 +287,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
 
 /*
 	Delay between EEPROM clock transitions.
-	No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
+	No extra delay is needed with 33MHz PCI, but 66MHz may change this.
 */
 
 #define eeprom_delay()	inl(ee_addr)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 7c00926..e9f6391 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -55,6 +55,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 
diff --git a/drivers/net/sk98lin/h/skdrv1st.h b/drivers/net/sk98lin/h/skdrv1st.h
index af34d7b..8d372b5 100644
--- a/drivers/net/sk98lin/h/skdrv1st.h
+++ b/drivers/net/sk98lin/h/skdrv1st.h
@@ -174,7 +174,7 @@ typedef struct s_AC	SK_AC;
 #if 0
 #define SK_TICKS_PER_SEC	HZ
 #else
-#define SK_TICKS_PER_SEC	CFG_HZ
+#define SK_TICKS_PER_SEC	CONFIG_SYS_HZ
 #endif
 
 #define	SK_MEM_MAPPED_IO
diff --git a/drivers/net/sk98lin/h/skgehw.h b/drivers/net/sk98lin/h/skgehw.h
index 52dc83f..8aad442 100644
--- a/drivers/net/sk98lin/h/skgehw.h
+++ b/drivers/net/sk98lin/h/skgehw.h
@@ -1107,10 +1107,10 @@ extern "C" {
 /*	Values of connector and PMD type comply to SysKonnect internal std */
 
 /*	B2_MAC_CFG	 8 bit	MAC Configuration / Chip Revision */
-#define CFG_CHIP_R_MSK	(0xf<<4)	/* Bit 7.. 4: Chip Revision */
+#define CONFIG_SYS_CHIP_R_MSK	(0xf<<4)	/* Bit 7.. 4: Chip Revision */
 									/* Bit 3.. 2:	reserved */
-#define CFG_DIS_M2_CLK	BIT_1S		/* Disable Clock for 2nd MAC */
-#define CFG_SNG_MAC		BIT_0S		/* MAC Config: 0=2 MACs / 1=1 MAC*/
+#define CONFIG_SYS_DIS_M2_CLK	BIT_1S		/* Disable Clock for 2nd MAC */
+#define CONFIG_SYS_SNG_MAC		BIT_0S		/* MAC Config: 0=2 MACs / 1=1 MAC*/
 
 /*	B2_CHIP_ID	 8 bit	Chip Identification Number */
 #define CHIP_ID_GENESIS	0x0a		/* Chip ID for GENESIS */
diff --git a/drivers/net/sk98lin/skgeinit.c b/drivers/net/sk98lin/skgeinit.c
index ab740c7..df63f27 100644
--- a/drivers/net/sk98lin/skgeinit.c
+++ b/drivers/net/sk98lin/skgeinit.c
@@ -1882,10 +1882,10 @@ SK_IOC	IoC)		/* IO context */
 
 	/* read number of MACs */
 	SK_IN8(IoC, B2_MAC_CFG, &Byte);
-	pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
+	pAC->GIni.GIMacsFound = (Byte & CONFIG_SYS_SNG_MAC) ? 1 : 2;
 
 	/* get Chip Revision Number */
-	pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);
+	pAC->GIni.GIChipRev = (SK_U8)((Byte & CONFIG_SYS_CHIP_R_MSK) >> 4);
 
 	/* get diff. PCI parameters */
 	SK_IN16(IoC, B0_CTST, &CtrlStat);
diff --git a/drivers/net/sk98lin/u-boot_compat.h b/drivers/net/sk98lin/u-boot_compat.h
index 1e385f8..cadf402 100644
--- a/drivers/net/sk98lin/u-boot_compat.h
+++ b/drivers/net/sk98lin/u-boot_compat.h
@@ -54,7 +54,7 @@
 #define EAGAIN				2
 #define EBUSY				3
 
-#define HZ				CFG_HZ
+#define HZ				CONFIG_SYS_HZ
 
 
 #define printk				printf
diff --git a/drivers/net/sk98lin/uboot_drv.c b/drivers/net/sk98lin/uboot_drv.c
index 205e7d2..0199b33 100644
--- a/drivers/net/sk98lin/uboot_drv.c
+++ b/drivers/net/sk98lin/uboot_drv.c
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 #include "h/skdrv1st.h"
 #include "h/skdrv2nd.h"
diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
index e8b235b..82abb02 100644
--- a/drivers/net/smc91111.c
+++ b/drivers/net/smc91111.c
@@ -383,7 +383,7 @@ static void smc_write_phy_register(byte phyreg, word phydata);
 
 static int poll4int (byte mask, int timeout)
 {
-	int tmo = get_timer (0) + timeout * CFG_HZ;
+	int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
 	int is_timeout = 0;
 	word old_bank = SMC_inw (BSR_REG);
 
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 0fff820..648c94c 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -57,6 +57,11 @@ static inline void reg_write(u32 addr, u32 val)
 #error "SMC911X: undefined bus width"
 #endif /* CONFIG_DRIVER_SMC911X_16_BIT */
 
+u32 pkt_data_pull(u32 addr) \
+	__attribute__ ((weak, alias ("reg_read")));
+void pkt_data_push(u32 addr, u32 val) \
+	__attribute__ ((weak, alias ("reg_write")));
+
 #define mdelay(n)       udelay((n)*1000)
 
 /* Below are the register offsets and bit definitions
@@ -641,7 +646,7 @@ int eth_send(volatile void *packet, int length)
 	tmplen = (length + 3) / 4;
 
 	while (tmplen--)
-		reg_write(TX_DATA_FIFO, *data++);
+		pkt_data_push(TX_DATA_FIFO, *data++);
 
 	/* wait for transmission */
 	while (!((reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
@@ -684,7 +689,7 @@ int eth_rx(void)
 
 		tmplen = (pktlen + 2+ 3) / 4;
 		while (tmplen--)
-			*data++ = reg_read(RX_DATA_FIFO);
+			*data++ = pkt_data_pull(RX_DATA_FIFO);
 
 		if (status & RX_STS_ES)
 			printf(DRIVERNAME
diff --git a/drivers/net/tigon3.c b/drivers/net/tigon3.c
index ab448b0..e4e004e 100644
--- a/drivers/net/tigon3.c
+++ b/drivers/net/tigon3.c
@@ -2247,7 +2247,7 @@ LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice)
 	REG_WR (pDevice, Grc.Mode, Value32);
 
 	/* Setup the timer prescalar register. */
-	REG_WR (pDevice, Grc.MiscCfg, 65 << 1);	/* Clock is alwasy 66Mhz. */
+	REG_WR (pDevice, Grc.MiscCfg, 65 << 1);	/* Clock is alwasy 66MHz. */
 
 	/* Set up the MBUF pool base address and size. */
 	REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 6e0f2c6..fbc9a6d 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -16,8 +16,8 @@
 #include <malloc.h>
 #include <net.h>
 #include <command.h>
+#include <tsec.h>
 
-#include "tsec.h"
 #include "miiphy.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -32,69 +32,12 @@ typedef volatile struct rtxbd {
 	rxbd8_t rxbd[PKTBUFSRX];
 } RTXBD;
 
-struct tsec_info_struct {
-	unsigned int phyaddr;
-	u32 flags;
-	unsigned int phyregidx;
-};
-
-/* The tsec_info structure contains 3 values which the
- * driver uses to determine how to operate a given ethernet
- * device. The information needed is:
- *  phyaddr - The address of the PHY which is attached to
- *	the given device.
- *
- *  flags - This variable indicates whether the device
- *	supports gigabit speed ethernet, and whether it should be
- *	in reduced mode.
- *
- *  phyregidx - This variable specifies which ethernet device
- *	controls the MII Management registers which are connected
- *	to the PHY.  For now, only TSEC1 (index 0) has
- *	access to the PHYs, so all of the entries have "0".
- *
- * The values specified in the table are taken from the board's
- * config file in include/configs/.  When implementing a new
- * board with ethernet capability, it is necessary to define:
- *   TSECn_PHY_ADDR
- *   TSECn_PHYIDX
- *
- * for n = 1,2,3, etc.  And for FEC:
- *   FEC_PHY_ADDR
- *   FEC_PHYIDX
- */
-static struct tsec_info_struct tsec_info[] = {
-#ifdef CONFIG_TSEC1
-	{TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX},
-#else
-	{0, 0, 0},
-#endif
-#ifdef CONFIG_TSEC2
-	{TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX},
-#else
-	{0, 0, 0},
-#endif
-#ifdef CONFIG_MPC85XX_FEC
-	{FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX},
-#else
-#ifdef CONFIG_TSEC3
-	{TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX},
-#else
-	{0, 0, 0},
-#endif
-#ifdef CONFIG_TSEC4
-	{TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX},
-#else
-	{0, 0, 0},
-#endif	/* CONFIG_TSEC4 */
-#endif	/* CONFIG_MPC85XX_FEC */
-};
-
-#define MAXCONTROLLERS	(4)
+#define MAXCONTROLLERS	(8)
 
 static int relocated = 0;
 
 static struct tsec_private *privlist[MAXCONTROLLERS];
+static int num_tsecs = 0;
 
 #ifdef __GNUC__
 static RTXBD rtx __attribute__ ((aligned(8)));
@@ -127,10 +70,51 @@ static int tsec_miiphy_read(char *devname, unsigned char addr,
 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
 #endif
 
+/* Default initializations for TSEC controllers. */
+
+static struct tsec_info_struct tsec_info[] = {
+#ifdef CONFIG_TSEC1
+	STD_TSEC_INFO(1),	/* TSEC1 */
+#endif
+#ifdef CONFIG_TSEC2
+	STD_TSEC_INFO(2),	/* TSEC2 */
+#endif
+#ifdef CONFIG_MPC85XX_FEC
+	{
+		.regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
+		.miiregs = (tsec_t *)(TSEC_BASE_ADDR),
+		.devname = CONFIG_MPC85XX_FEC_NAME,
+		.phyaddr = FEC_PHY_ADDR,
+		.flags = FEC_FLAGS
+	},			/* FEC */
+#endif
+#ifdef CONFIG_TSEC3
+	STD_TSEC_INFO(3),	/* TSEC3 */
+#endif
+#ifdef CONFIG_TSEC4
+	STD_TSEC_INFO(4),	/* TSEC4 */
+#endif
+};
+
+int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
+{
+	int i;
+
+	for (i = 0; i < num; i++)
+		tsec_initialize(bis, &tsecs[i]);
+
+	return 0;
+}
+
+int tsec_standard_init(bd_t *bis)
+{
+	return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
+}
+
 /* Initialize device structure. Returns success if PHY
  * initialization succeeded (i.e. if it recognizes the PHY)
  */
-int tsec_initialize(bd_t * bis, int index, char *devname)
+int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
 {
 	struct eth_device *dev;
 	int i;
@@ -148,16 +132,14 @@ int tsec_initialize(bd_t * bis, int index, char *devname)
 	if (NULL == priv)
 		return 0;
 
-	privlist[index] = priv;
-	priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
-	priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
-					    tsec_info[index].phyregidx *
-					    TSEC_SIZE);
+	privlist[num_tsecs++] = priv;
+	priv->regs = tsec_info->regs;
+	priv->phyregs = tsec_info->miiregs;
 
-	priv->phyaddr = tsec_info[index].phyaddr;
-	priv->flags = tsec_info[index].flags;
+	priv->phyaddr = tsec_info->phyaddr;
+	priv->flags = tsec_info->flags;
 
-	sprintf(dev->name, devname);
+	sprintf(dev->name, tsec_info->devname);
 	dev->iobase = 0;
 	dev->priv = priv;
 	dev->init = tsec_init;
@@ -232,64 +214,84 @@ int tsec_init(struct eth_device *dev, bd_t * bd)
 
 	/* If there's no link, fail */
 	return (priv->link ? 0 : -1);
-
 }
 
-/* Write value to the device's PHY through the registers
- * specified in priv, modifying the register specified in regnum.
- * It will wait for the write to be done (or for a timeout to
- * expire) before exiting
- */
-void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value)
+/* Writes the given phy's reg with value, using the specified MDIO regs */
+static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr,
+		uint reg, uint value)
 {
-	volatile tsec_t *regbase = priv->phyregs;
 	int timeout = 1000000;
 
-	regbase->miimadd = (phyid << 8) | regnum;
-	regbase->miimcon = value;
+	phyregs->miimadd = (addr << 8) | reg;
+	phyregs->miimcon = value;
 	asm("sync");
 
 	timeout = 1000000;
-	while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
+	while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
 }
 
-/* #define to provide old write_phy_reg functionality without duplicating code */
-#define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value)
+
+/* Provide the default behavior of writing the PHY of this ethernet device */
+#define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
 
 /* Reads register regnum on the device's PHY through the
- * registers specified in priv.	 It lowers and raises the read
+ * specified registers.	 It lowers and raises the read
  * command, and waits for the data to become valid (miimind
  * notvalid bit cleared), and the bus to cease activity (miimind
  * busy bit cleared), and then returns the value
  */
-uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum)
+uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
 {
 	uint value;
-	volatile tsec_t *regbase = priv->phyregs;
 
 	/* Put the address of the phy, and the register
 	 * number into MIIMADD */
-	regbase->miimadd = (phyid << 8) | regnum;
+	phyregs->miimadd = (phyid << 8) | regnum;
 
 	/* Clear the command register, and wait */
-	regbase->miimcom = 0;
+	phyregs->miimcom = 0;
 	asm("sync");
 
 	/* Initiate a read command, and wait */
-	regbase->miimcom = MIIM_READ_COMMAND;
+	phyregs->miimcom = MIIM_READ_COMMAND;
 	asm("sync");
 
 	/* Wait for the the indication that the read is done */
-	while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
+	while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 
 	/* Grab the value read from the PHY */
-	value = regbase->miimstat;
+	value = phyregs->miimstat;
 
 	return value;
 }
 
 /* #define to provide old read_phy_reg functionality without duplicating code */
-#define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum)
+#define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
+
+#define TBIANA_SETTINGS ( \
+		TBIANA_ASYMMETRIC_PAUSE \
+		| TBIANA_SYMMETRIC_PAUSE \
+		| TBIANA_FULL_DUPLEX \
+		)
+
+#define TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_ANEG_ENABLE \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+/* Configure the TBI for SGMII operation */
+static void tsec_configure_serdes(struct tsec_private *priv)
+{
+	/* Access TBI PHY registers at given TSEC register offset as opposed to the
+	 * register offset used for external PHY accesses */
+	tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA,
+			TBIANA_SETTINGS);
+	tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON,
+			TBICON_CLK_SELECT);
+	tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR,
+			TBICR_SETTINGS);
+}
 
 /* Discover which PHY is attached to the device, and configure it
  * properly.  If the PHY is not recognized, then return 0
@@ -299,12 +301,12 @@ static int init_phy(struct eth_device *dev)
 {
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
 	struct phy_info *curphy;
-	volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
+	volatile tsec_t *phyregs = priv->phyregs;
+	volatile tsec_t *regs = priv->regs;
 
 	/* Assign a Physical address to the TBI */
-	regs->tbipa = CFG_TBIPA_VALUE;
-	regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
-	regs->tbipa = CFG_TBIPA_VALUE;
+	regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
+	phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE;
 	asm("sync");
 
 	/* Reset MII (due to new addresses) */
@@ -328,6 +330,9 @@ static int init_phy(struct eth_device *dev)
 		return 0;
 	}
 
+	if (regs->ecntrl & ECNTRL_SGMII_MODE)
+		tsec_configure_serdes(priv);
+
 	priv->phyinfo = curphy;
 
 	phy_run_commands(priv, priv->phyinfo->config);
@@ -1157,6 +1162,57 @@ struct phy_info phy_info_M88E1118 = {
 		},
 };
 
+/*
+ *  Since to access LED register we need do switch the page, we
+ * do LED configuring in the miim_read-like function as follows
+ */
+uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
+{
+	uint pg;
+
+	/* Switch the page to access the led register */
+	pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
+	write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
+
+	/* Configure leds */
+	write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
+		      MIIM_88E1121_PHY_LED_DEF);
+
+	/* Restore the page pointer */
+	write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
+	return 0;
+}
+
+struct phy_info phy_info_M88E1121R = {
+	0x01410cb,
+	"Marvell 88E1121R",
+	4,
+	(struct phy_cmd[]){	/* config */
+			   /* Reset and configure the PHY */
+			   {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+			   {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+			   {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+			   /* Configure leds */
+			   {MIIM_88E1121_PHY_LED_CTRL, miim_read,
+			    &mii_88E1121_set_led},
+			   {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+			   /* Disable IRQs and de-assert interrupt */
+			   {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
+			   {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
+			   {miim_end,}
+			   },
+	(struct phy_cmd[]){	/* startup */
+			   /* Status is read once to clear old link state */
+			   {MIIM_STATUS, miim_read, NULL},
+			   {MIIM_STATUS, miim_read, &mii_parse_sr},
+			   {MIIM_STATUS, miim_read, &mii_parse_link},
+			   {miim_end,}
+			   },
+	(struct phy_cmd[]){	/* shutdown */
+			   {miim_end,}
+			   },
+};
+
 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
 {
 	uint mii_data = read_phy_reg(priv, mii_reg);
@@ -1304,15 +1360,17 @@ struct phy_info phy_info_VSC8601 = {
 				/* Override PHY config settings */
 				/* Configure some basic stuff */
 				{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
-#ifdef CFG_VSC8601_SKEWFIX
+#ifdef CONFIG_SYS_VSC8601_SKEWFIX
 				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
-#if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX)
+#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
 				{MIIM_EXT_PAGE_ACCESS,1,NULL},
-#define VSC8101_SKEW	(CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12)
+#define VSC8101_SKEW	(CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12)
 				{MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
 				{MIIM_EXT_PAGE_ACCESS,0,NULL},
 #endif
 #endif
+				{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+				{MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
 				{miim_end,}
 				 },
 		(struct phy_cmd[]){     /* startup */
@@ -1522,6 +1580,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_M88E1011S,
 	&phy_info_M88E1111S,
 	&phy_info_M88E1118,
+	&phy_info_M88E1121R,
 	&phy_info_M88E1145,
 	&phy_info_M88E1149S,
 	&phy_info_dm9161,
@@ -1670,7 +1729,7 @@ static int tsec_miiphy_read(char *devname, unsigned char addr,
 		return -1;
 	}
 
-	ret = (unsigned short)read_any_phy_reg(priv, addr, reg);
+	ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
 	*value = ret;
 
 	return 0;
@@ -1692,7 +1751,7 @@ static int tsec_miiphy_write(char *devname, unsigned char addr,
 		return -1;
 	}
 
-	write_any_phy_reg(priv, addr, reg, value);
+	tsec_local_mdio_write(priv->phyregs, addr, reg, value);
 
 	return 0;
 }
diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
deleted file mode 100644
index 6a2338b..0000000
--- a/drivers/net/tsec.h
+++ /dev/null
@@ -1,579 +0,0 @@
-/*
- *  tsec.h
- *
- *  Driver for the Motorola Triple Speed Ethernet Controller
- *
- *  This software may be used and distributed according to the
- *  terms of the GNU Public License, Version 2, incorporated
- *  herein by reference.
- *
- * Copyright 2004, 2007 Freescale Semiconductor, Inc.
- * (C) Copyright 2003, Motorola, Inc.
- * maintained by Xianghua Xiao (x.xiao@motorola.com)
- * author Andy Fleming
- *
- */
-
-#ifndef __TSEC_H
-#define __TSEC_H
-
-#include <net.h>
-#include <config.h>
-
-#ifndef CFG_TSEC1_OFFSET
-    #define CFG_TSEC1_OFFSET	(0x24000)
-#endif
-
-#define TSEC_SIZE	0x01000
-
-/* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
-    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
-#elif defined(CONFIG_MPC83XX)
-    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
-#endif
-
-
-#define MAC_ADDR_LEN 6
-
-/* #define TSEC_TIMEOUT	1000000 */
-#define TSEC_TIMEOUT 1000
-#define TOUT_LOOP	1000000
-
-#define PHY_AUTONEGOTIATE_TIMEOUT	5000 /* in ms */
-
-/* MAC register bits */
-#define MACCFG1_SOFT_RESET	0x80000000
-#define MACCFG1_RESET_RX_MC	0x00080000
-#define MACCFG1_RESET_TX_MC	0x00040000
-#define MACCFG1_RESET_RX_FUN	0x00020000
-#define	MACCFG1_RESET_TX_FUN	0x00010000
-#define MACCFG1_LOOPBACK	0x00000100
-#define MACCFG1_RX_FLOW		0x00000020
-#define MACCFG1_TX_FLOW		0x00000010
-#define MACCFG1_SYNCD_RX_EN	0x00000008
-#define MACCFG1_RX_EN		0x00000004
-#define MACCFG1_SYNCD_TX_EN	0x00000002
-#define MACCFG1_TX_EN		0x00000001
-
-#define MACCFG2_INIT_SETTINGS	0x00007205
-#define MACCFG2_FULL_DUPLEX	0x00000001
-#define MACCFG2_IF		0x00000300
-#define MACCFG2_GMII		0x00000200
-#define MACCFG2_MII		0x00000100
-
-#define ECNTRL_INIT_SETTINGS	0x00001000
-#define ECNTRL_TBI_MODE		0x00000020
-#define ECNTRL_R100		0x00000008
-#define ECNTRL_SGMII_MODE	0x00000002
-
-#define miim_end -2
-#define miim_read -1
-
-#ifndef CFG_TBIPA_VALUE
-    #define CFG_TBIPA_VALUE	0x1f
-#endif
-#define MIIMCFG_INIT_VALUE	0x00000003
-#define MIIMCFG_RESET		0x80000000
-
-#define MIIMIND_BUSY		0x00000001
-#define MIIMIND_NOTVALID	0x00000004
-
-#define MIIM_CONTROL		0x00
-#define MIIM_CONTROL_RESET	0x00009140
-#define MIIM_CONTROL_INIT	0x00001140
-#define MIIM_CONTROL_RESTART	0x00001340
-#define MIIM_ANEN		0x00001000
-
-#define MIIM_CR			0x00
-#define MIIM_CR_RST		0x00008000
-#define MIIM_CR_INIT		0x00001000
-
-#define MIIM_STATUS		0x1
-#define MIIM_STATUS_AN_DONE	0x00000020
-#define MIIM_STATUS_LINK	0x0004
-#define PHY_BMSR_AUTN_ABLE	0x0008
-#define PHY_BMSR_AUTN_COMP	0x0020
-
-#define MIIM_PHYIR1		0x2
-#define MIIM_PHYIR2		0x3
-
-#define MIIM_ANAR		0x4
-#define MIIM_ANAR_INIT		0x1e1
-
-#define MIIM_TBI_ANLPBPA	0x5
-#define MIIM_TBI_ANLPBPA_HALF	0x00000040
-#define MIIM_TBI_ANLPBPA_FULL	0x00000020
-
-#define MIIM_TBI_ANEX		0x6
-#define MIIM_TBI_ANEX_NP	0x00000004
-#define MIIM_TBI_ANEX_PRX	0x00000002
-
-#define MIIM_GBIT_CONTROL	0x9
-#define MIIM_GBIT_CONTROL_INIT	0xe00
-
-#define MIIM_EXT_PAGE_ACCESS	0x1f
-
-/* Broadcom BCM54xx -- taken from linux sungem_phy */
-#define MIIM_BCM54xx_AUXSTATUS			0x19
-#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK	0x0700
-#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT	8
-
-/* Cicada Auxiliary Control/Status Register */
-#define MIIM_CIS8201_AUX_CONSTAT	0x1c
-#define MIIM_CIS8201_AUXCONSTAT_INIT	0x0004
-#define MIIM_CIS8201_AUXCONSTAT_DUPLEX	0x0020
-#define MIIM_CIS8201_AUXCONSTAT_SPEED	0x0018
-#define MIIM_CIS8201_AUXCONSTAT_GBIT	0x0010
-#define MIIM_CIS8201_AUXCONSTAT_100	0x0008
-
-/* Cicada Extended Control Register 1 */
-#define MIIM_CIS8201_EXT_CON1		0x17
-#define MIIM_CIS8201_EXTCON1_INIT	0x0000
-
-/* Cicada 8204 Extended PHY Control Register 1 */
-#define MIIM_CIS8204_EPHY_CON		0x17
-#define MIIM_CIS8204_EPHYCON_INIT	0x0006
-#define MIIM_CIS8204_EPHYCON_RGMII	0x1100
-
-/* Cicada 8204 Serial LED Control Register */
-#define MIIM_CIS8204_SLED_CON		0x1b
-#define MIIM_CIS8204_SLEDCON_INIT	0x1115
-
-#define MIIM_GBIT_CON		0x09
-#define MIIM_GBIT_CON_ADVERT	0x0e00
-
-/* Entry for Vitesse VSC8244 regs starts here */
-/* Vitesse VSC8244 Auxiliary Control/Status Register */
-#define MIIM_VSC8244_AUX_CONSTAT	0x1c
-#define MIIM_VSC8244_AUXCONSTAT_INIT	0x0000
-#define MIIM_VSC8244_AUXCONSTAT_DUPLEX	0x0020
-#define MIIM_VSC8244_AUXCONSTAT_SPEED	0x0018
-#define MIIM_VSC8244_AUXCONSTAT_GBIT	0x0010
-#define MIIM_VSC8244_AUXCONSTAT_100	0x0008
-#define MIIM_CONTROL_INIT_LOOPBACK	0x4000
-
-/* Vitesse VSC8244 Extended PHY Control Register 1 */
-#define MIIM_VSC8244_EPHY_CON		0x17
-#define MIIM_VSC8244_EPHYCON_INIT	0x0006
-
-/* Vitesse VSC8244 Serial LED Control Register */
-#define MIIM_VSC8244_LED_CON		0x1b
-#define MIIM_VSC8244_LEDCON_INIT	0xF011
-
-/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
-/* Vitesse VSC8601 Extended PHY Control Register 1 */
-#define MIIM_VSC8601_EPHY_CON		0x17
-#define MIIM_VSC8601_EPHY_CON_INIT_SKEW	0x1120
-#define MIIM_VSC8601_SKEW_CTRL		0x1c
-
-/* 88E1011 PHY Status Register */
-#define MIIM_88E1011_PHY_STATUS		0x11
-#define MIIM_88E1011_PHYSTAT_SPEED	0xc000
-#define MIIM_88E1011_PHYSTAT_GBIT	0x8000
-#define MIIM_88E1011_PHYSTAT_100	0x4000
-#define MIIM_88E1011_PHYSTAT_DUPLEX	0x2000
-#define MIIM_88E1011_PHYSTAT_SPDDONE	0x0800
-#define MIIM_88E1011_PHYSTAT_LINK	0x0400
-
-#define MIIM_88E1011_PHY_SCR		0x10
-#define MIIM_88E1011_PHY_MDI_X_AUTO	0x0060
-
-/* 88E1111 PHY LED Control Register */
-#define MIIM_88E1111_PHY_LED_CONTROL	24
-#define MIIM_88E1111_PHY_LED_DIRECT	0x4100
-#define MIIM_88E1111_PHY_LED_COMBINE	0x411C
-
-/* 88E1145 Extended PHY Specific Control Register */
-#define MIIM_88E1145_PHY_EXT_CR 20
-#define MIIM_M88E1145_RGMII_RX_DELAY	0x0080
-#define MIIM_M88E1145_RGMII_TX_DELAY	0x0002
-
-#define MIIM_88E1145_PHY_PAGE	29
-#define MIIM_88E1145_PHY_CAL_OV 30
-
-/* RTL8211B PHY Status Register */
-#define MIIM_RTL8211B_PHY_STATUS	0x11
-#define MIIM_RTL8211B_PHYSTAT_SPEED	0xc000
-#define MIIM_RTL8211B_PHYSTAT_GBIT	0x8000
-#define MIIM_RTL8211B_PHYSTAT_100	0x4000
-#define MIIM_RTL8211B_PHYSTAT_DUPLEX	0x2000
-#define MIIM_RTL8211B_PHYSTAT_SPDDONE	0x0800
-#define MIIM_RTL8211B_PHYSTAT_LINK	0x0400
-
-/* DM9161 Control register values */
-#define MIIM_DM9161_CR_STOP	0x0400
-#define MIIM_DM9161_CR_RSTAN	0x1200
-
-#define MIIM_DM9161_SCR		0x10
-#define MIIM_DM9161_SCR_INIT	0x0610
-
-/* DM9161 Specified Configuration and Status Register */
-#define MIIM_DM9161_SCSR	0x11
-#define MIIM_DM9161_SCSR_100F	0x8000
-#define MIIM_DM9161_SCSR_100H	0x4000
-#define MIIM_DM9161_SCSR_10F	0x2000
-#define MIIM_DM9161_SCSR_10H	0x1000
-
-/* DM9161 10BT Configuration/Status */
-#define MIIM_DM9161_10BTCSR	0x12
-#define MIIM_DM9161_10BTCSR_INIT	0x7800
-
-/* LXT971 Status 2 registers */
-#define MIIM_LXT971_SR2		     0x11  /* Status Register 2  */
-#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
-#define MIIM_LXT971_SR2_10HDX	   0x0000  /*  10 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_10FDX	   0x0200  /*  10 Mbit full duplex selected */
-#define MIIM_LXT971_SR2_100HDX	   0x4000  /* 100 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_100FDX	   0x4200  /* 100 Mbit full duplex selected */
-
-/* DP83865 Control register values */
-#define MIIM_DP83865_CR_INIT	0x9200
-
-/* DP83865 Link and Auto-Neg Status Register */
-#define MIIM_DP83865_LANR	0x11
-#define MIIM_DP83865_SPD_MASK	0x0018
-#define MIIM_DP83865_SPD_1000	0x0010
-#define MIIM_DP83865_SPD_100	0x0008
-#define MIIM_DP83865_DPX_FULL	0x0002
-
-#define MIIM_READ_COMMAND	0x00000001
-
-#define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN
-
-#define MINFLR_INIT_SETTINGS	0x00000040
-
-#define DMACTRL_INIT_SETTINGS	0x000000c3
-#define DMACTRL_GRS		0x00000010
-#define DMACTRL_GTS		0x00000008
-
-#define TSTAT_CLEAR_THALT	0x80000000
-#define RSTAT_CLEAR_RHALT	0x00800000
-
-
-#define IEVENT_INIT_CLEAR	0xffffffff
-#define IEVENT_BABR		0x80000000
-#define IEVENT_RXC		0x40000000
-#define IEVENT_BSY		0x20000000
-#define IEVENT_EBERR		0x10000000
-#define IEVENT_MSRO		0x04000000
-#define IEVENT_GTSC		0x02000000
-#define IEVENT_BABT		0x01000000
-#define IEVENT_TXC		0x00800000
-#define IEVENT_TXE		0x00400000
-#define IEVENT_TXB		0x00200000
-#define IEVENT_TXF		0x00100000
-#define IEVENT_IE		0x00080000
-#define IEVENT_LC		0x00040000
-#define IEVENT_CRL		0x00020000
-#define IEVENT_XFUN		0x00010000
-#define IEVENT_RXB0		0x00008000
-#define IEVENT_GRSC		0x00000100
-#define IEVENT_RXF0		0x00000080
-
-#define IMASK_INIT_CLEAR	0x00000000
-#define IMASK_TXEEN		0x00400000
-#define IMASK_TXBEN		0x00200000
-#define IMASK_TXFEN		0x00100000
-#define IMASK_RXFEN0		0x00000080
-
-
-/* Default Attribute fields */
-#define ATTR_INIT_SETTINGS     0x000000c0
-#define ATTRELI_INIT_SETTINGS  0x00000000
-
-
-/* TxBD status field bits */
-#define TXBD_READY		0x8000
-#define TXBD_PADCRC		0x4000
-#define TXBD_WRAP		0x2000
-#define TXBD_INTERRUPT		0x1000
-#define TXBD_LAST		0x0800
-#define TXBD_CRC		0x0400
-#define TXBD_DEF		0x0200
-#define TXBD_HUGEFRAME		0x0080
-#define TXBD_LATECOLLISION	0x0080
-#define TXBD_RETRYLIMIT		0x0040
-#define	TXBD_RETRYCOUNTMASK	0x003c
-#define TXBD_UNDERRUN		0x0002
-#define TXBD_STATS		0x03ff
-
-/* RxBD status field bits */
-#define RXBD_EMPTY		0x8000
-#define RXBD_RO1		0x4000
-#define RXBD_WRAP		0x2000
-#define RXBD_INTERRUPT		0x1000
-#define RXBD_LAST		0x0800
-#define RXBD_FIRST		0x0400
-#define RXBD_MISS		0x0100
-#define RXBD_BROADCAST		0x0080
-#define RXBD_MULTICAST		0x0040
-#define RXBD_LARGE		0x0020
-#define RXBD_NONOCTET		0x0010
-#define RXBD_SHORT		0x0008
-#define RXBD_CRCERR		0x0004
-#define RXBD_OVERRUN		0x0002
-#define RXBD_TRUNCATED		0x0001
-#define RXBD_STATS		0x003f
-
-typedef struct txbd8
-{
-	ushort	     status;	     /* Status Fields */
-	ushort	     length;	     /* Buffer length */
-	uint	     bufPtr;	     /* Buffer Pointer */
-} txbd8_t;
-
-typedef struct rxbd8
-{
-	ushort	     status;	     /* Status Fields */
-	ushort	     length;	     /* Buffer Length */
-	uint	     bufPtr;	     /* Buffer Pointer */
-} rxbd8_t;
-
-typedef struct rmon_mib
-{
-	/* Transmit and Receive Counters */
-	uint	tr64;		/* Transmit and Receive 64-byte Frame Counter */
-	uint	tr127;		/* Transmit and Receive 65-127 byte Frame Counter */
-	uint	tr255;		/* Transmit and Receive 128-255 byte Frame Counter */
-	uint	tr511;		/* Transmit and Receive 256-511 byte Frame Counter */
-	uint	tr1k;		/* Transmit and Receive 512-1023 byte Frame Counter */
-	uint	trmax;		/* Transmit and Receive 1024-1518 byte Frame Counter */
-	uint	trmgv;		/* Transmit and Receive 1519-1522 byte Good VLAN Frame */
-	/* Receive Counters */
-	uint	rbyt;		/* Receive Byte Counter */
-	uint	rpkt;		/* Receive Packet Counter */
-	uint	rfcs;		/* Receive FCS Error Counter */
-	uint	rmca;		/* Receive Multicast Packet (Counter) */
-	uint	rbca;		/* Receive Broadcast Packet */
-	uint	rxcf;		/* Receive Control Frame Packet */
-	uint	rxpf;		/* Receive Pause Frame Packet */
-	uint	rxuo;		/* Receive Unknown OP Code */
-	uint	raln;		/* Receive Alignment Error */
-	uint	rflr;		/* Receive Frame Length Error */
-	uint	rcde;		/* Receive Code Error */
-	uint	rcse;		/* Receive Carrier Sense Error */
-	uint	rund;		/* Receive Undersize Packet */
-	uint	rovr;		/* Receive Oversize Packet */
-	uint	rfrg;		/* Receive Fragments */
-	uint	rjbr;		/* Receive Jabber */
-	uint	rdrp;		/* Receive Drop */
-	/* Transmit Counters */
-	uint	tbyt;		/* Transmit Byte Counter */
-	uint	tpkt;		/* Transmit Packet */
-	uint	tmca;		/* Transmit Multicast Packet */
-	uint	tbca;		/* Transmit Broadcast Packet */
-	uint	txpf;		/* Transmit Pause Control Frame */
-	uint	tdfr;		/* Transmit Deferral Packet */
-	uint	tedf;		/* Transmit Excessive Deferral Packet */
-	uint	tscl;		/* Transmit Single Collision Packet */
-	/* (0x2_n700) */
-	uint	tmcl;		/* Transmit Multiple Collision Packet */
-	uint	tlcl;		/* Transmit Late Collision Packet */
-	uint	txcl;		/* Transmit Excessive Collision Packet */
-	uint	tncl;		/* Transmit Total Collision */
-
-	uint	res2;
-
-	uint	tdrp;		/* Transmit Drop Frame */
-	uint	tjbr;		/* Transmit Jabber Frame */
-	uint	tfcs;		/* Transmit FCS Error */
-	uint	txcf;		/* Transmit Control Frame */
-	uint	tovr;		/* Transmit Oversize Frame */
-	uint	tund;		/* Transmit Undersize Frame */
-	uint	tfrg;		/* Transmit Fragments Frame */
-	/* General Registers */
-	uint	car1;		/* Carry Register One */
-	uint	car2;		/* Carry Register Two */
-	uint	cam1;		/* Carry Register One Mask */
-	uint	cam2;		/* Carry Register Two Mask */
-} rmon_mib_t;
-
-typedef struct tsec_hash_regs
-{
-	uint	iaddr0;		/* Individual Address Register 0 */
-	uint	iaddr1;		/* Individual Address Register 1 */
-	uint	iaddr2;		/* Individual Address Register 2 */
-	uint	iaddr3;		/* Individual Address Register 3 */
-	uint	iaddr4;		/* Individual Address Register 4 */
-	uint	iaddr5;		/* Individual Address Register 5 */
-	uint	iaddr6;		/* Individual Address Register 6 */
-	uint	iaddr7;		/* Individual Address Register 7 */
-	uint	res1[24];
-	uint	gaddr0;		/* Group Address Register 0 */
-	uint	gaddr1;		/* Group Address Register 1 */
-	uint	gaddr2;		/* Group Address Register 2 */
-	uint	gaddr3;		/* Group Address Register 3 */
-	uint	gaddr4;		/* Group Address Register 4 */
-	uint	gaddr5;		/* Group Address Register 5 */
-	uint	gaddr6;		/* Group Address Register 6 */
-	uint	gaddr7;		/* Group Address Register 7 */
-	uint	res2[24];
-} tsec_hash_t;
-
-typedef struct tsec
-{
-	/* General Control and Status Registers (0x2_n000) */
-	uint	res000[4];
-
-	uint	ievent;		/* Interrupt Event */
-	uint	imask;		/* Interrupt Mask */
-	uint	edis;		/* Error Disabled */
-	uint	res01c;
-	uint	ecntrl;		/* Ethernet Control */
-	uint	minflr;		/* Minimum Frame Length */
-	uint	ptv;		/* Pause Time Value */
-	uint	dmactrl;	/* DMA Control */
-	uint	tbipa;		/* TBI PHY Address */
-
-	uint	res034[3];
-	uint	res040[48];
-
-	/* Transmit Control and Status Registers (0x2_n100) */
-	uint	tctrl;		/* Transmit Control */
-	uint	tstat;		/* Transmit Status */
-	uint	res108;
-	uint	tbdlen;		/* Tx BD Data Length */
-	uint	res110[5];
-	uint	ctbptr;		/* Current TxBD Pointer */
-	uint	res128[23];
-	uint	tbptr;		/* TxBD Pointer */
-	uint	res188[30];
-	/* (0x2_n200) */
-	uint	res200;
-	uint	tbase;		/* TxBD Base Address */
-	uint	res208[42];
-	uint	ostbd;		/* Out of Sequence TxBD */
-	uint	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
-	uint	res2b8[18];
-
-	/* Receive Control and Status Registers (0x2_n300) */
-	uint	rctrl;		/* Receive Control */
-	uint	rstat;		/* Receive Status */
-	uint	res308;
-	uint	rbdlen;		/* RxBD Data Length */
-	uint	res310[4];
-	uint	res320;
-	uint	crbptr;	/* Current Receive Buffer Pointer */
-	uint	res328[6];
-	uint	mrblr;	/* Maximum Receive Buffer Length */
-	uint	res344[16];
-	uint	rbptr;	/* RxBD Pointer */
-	uint	res388[30];
-	/* (0x2_n400) */
-	uint	res400;
-	uint	rbase;	/* RxBD Base Address */
-	uint	res408[62];
-
-	/* MAC Registers (0x2_n500) */
-	uint	maccfg1;	/* MAC Configuration #1 */
-	uint	maccfg2;	/* MAC Configuration #2 */
-	uint	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
-	uint	hafdup;		/* Half-duplex */
-	uint	maxfrm;		/* Maximum Frame */
-	uint	res514;
-	uint	res518;
-
-	uint	res51c;
-
-	uint	miimcfg;	/* MII Management: Configuration */
-	uint	miimcom;	/* MII Management: Command */
-	uint	miimadd;	/* MII Management: Address */
-	uint	miimcon;	/* MII Management: Control */
-	uint	miimstat;	/* MII Management: Status */
-	uint	miimind;	/* MII Management: Indicators */
-
-	uint	res538;
-
-	uint	ifstat;		/* Interface Status */
-	uint	macstnaddr1;	/* Station Address, part 1 */
-	uint	macstnaddr2;	/* Station Address, part 2 */
-	uint	res548[46];
-
-	/* (0x2_n600) */
-	uint	res600[32];
-
-	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
-	rmon_mib_t	rmon;
-	uint	res740[48];
-
-	/* Hash Function Registers (0x2_n800) */
-	tsec_hash_t	hash;
-
-	uint	res900[128];
-
-	/* Pattern Registers (0x2_nb00) */
-	uint	resb00[62];
-	uint	attr;	   /* Default Attribute Register */
-	uint	attreli;	   /* Default Attribute Extract Length and Index */
-
-	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
-	uint	resc00[256];
-} tsec_t;
-
-#define TSEC_GIGABIT (1)
-
-/* This flag currently only has
- * meaning if we're using the eTSEC */
-#define TSEC_REDUCED (1 << 1)
-
-struct tsec_private {
-	volatile tsec_t *regs;
-	volatile tsec_t *phyregs;
-	struct phy_info *phyinfo;
-	uint phyaddr;
-	u32 flags;
-	uint link;
-	uint duplexity;
-	uint speed;
-};
-
-
-/*
- * struct phy_cmd:  A command for reading or writing a PHY register
- *
- * mii_reg:  The register to read or write
- *
- * mii_data:  For writes, the value to put in the register.
- *	A value of -1 indicates this is a read.
- *
- * funct: A function pointer which is invoked for each command.
- *	For reads, this function will be passed the value read
- *	from the PHY, and process it.
- *	For writes, the result of this function will be written
- *	to the PHY register
- */
-struct phy_cmd {
-	uint mii_reg;
-	uint mii_data;
-	uint (*funct) (uint mii_reg, struct tsec_private * priv);
-};
-
-/* struct phy_info: a structure which defines attributes for a PHY
- *
- * id will contain a number which represents the PHY.  During
- * startup, the driver will poll the PHY to find out what its
- * UID--as defined by registers 2 and 3--is.  The 32-bit result
- * gotten from the PHY will be shifted right by "shift" bits to
- * discard any bits which may change based on revision numbers
- * unimportant to functionality
- *
- * The struct phy_cmd entries represent pointers to an arrays of
- * commands which tell the driver what to do to the PHY.
- */
-struct phy_info {
-	uint id;
-	char *name;
-	uint shift;
-	/* Called to configure the PHY, and modify the controller
-	 * based on the results */
-	struct phy_cmd *config;
-
-	/* Called when starting up the controller */
-	struct phy_cmd *startup;
-
-	/* Called when bringing down the controller */
-	struct phy_cmd *shutdown;
-};
-
-#endif /* __TSEC_H */
diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c
index 2534097..079354a 100644
--- a/drivers/net/tsi108_eth.c
+++ b/drivers/net/tsi108_eth.c
@@ -34,6 +34,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/cache.h>
 
 #ifdef DEBUG
@@ -53,7 +54,7 @@ printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
 #define RX_PRINT_ERRORS
 #define TX_PRINT_ERRORS
 
-#define ETH_BASE	(CFG_TSI108_CSR_BASE + 0x6000)
+#define ETH_BASE	(CONFIG_SYS_TSI108_CSR_BASE + 0x6000)
 
 #define ETH_PORT_OFFSET	0x400
 
diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c
index d87638c..9ea5ac2 100644
--- a/drivers/net/uli526x.c
+++ b/drivers/net/uli526x.c
@@ -16,6 +16,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 #include <miiphy.h>
diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
index 4e7259f..ada42c4 100644
--- a/drivers/net/vsc7385.c
+++ b/drivers/net/vsc7385.c
@@ -35,13 +35,13 @@ int vsc7385_upload_firmware(void *firmware, unsigned int size)
 	u8 *fw = firmware;
 	unsigned int i;
 
-	u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050);
-	u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040);
-	u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044);
-	u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048);
-	u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070);
+	u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050);
+	u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040);
+	u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044);
+	u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048);
+	u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070);
 #ifdef DEBUG
-	u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060);
+	u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060);
 #endif
 
 	out_be32(gloreset, 3);
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 9ba4096..0e96ef1 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -70,10 +70,10 @@ typedef struct {
 
 static xemaclite emaclite;
 
-static char etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
+static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
 
 /* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
-#ifdef CFG_ENV_IS_NOWHERE
+#ifdef CONFIG_ENV_IS_NOWHERE
 static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
 #else
 static u8 emacaddr[ENET_ADDR_LENGTH];