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authorJohn Rigby <jrigby@freescale.com>2008-08-28 13:17:07 -0600
committerJohn Rigby <jrigby@freescale.com>2008-08-28 13:36:43 -0600
commit8a490422bed685c9491274ec997f62061d88620b (patch)
treed5d8b3471cacd352bf419431c619b742f5aa8589 /drivers/net
parent33aa4eac66b71c797bbc13b3afe432a2132947d4 (diff)
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ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon
MPC5121 rev 2 silicon has a new register for controlling how long CS is asserted after deassertion of ALE in multiplexed mode. The default is to assert CS together with ALE. The alternative is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE. The default is wrong for the NOR flash and CPLD on the ADS5121. This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD) it does so conditionally based on silicon rev 2.0 or greater. Signed-off-by: Martha J Marx <mmarx@silicontkx.com> Signed-off-by: John Rigby <jrigby@freescale.com>
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