Merge branch 'next' of git://git.denx.de/u-boot

* 'next' of git://git.denx.de/u-boot:
  MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
  doc: cleanup - move board READMEs into respective board directories
  net: sh_eth: add support for SH7757's GETHER
  net: sh_eth: modify the definitions of regsiter
  net: sh_eth: add SH_ETH_TYPE_ condition
  net: sh_eth: clean up for the SH7757's code
  net: fec_mxc: Fix MDC for xMII
  net: fec_mxc: Fix setting of RCR for xMII
  net: nfs: make NFS_TIMEOUT configurable
  net: Inline the new eth_setenv_enetaddr_by_index function
  net: allow setting env enetaddr from net device setting
  net/designware: Consecutive writes to the same register to be avoided
  CACHE: net: asix: Fix asix driver to work with data cache on
  net: phy: micrel: make ksz9021 phy accessible
  net: abort network initialization if the PHY driver fails
  phylib: phy_startup() should return an error code on failure
  net: tftp: fix type of block arg to store_block

Signed-off-by: Wolfgang Denk <wd@denx.de>

10 files changed, 361 insertions, 248 deletions

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 326d550..bf21a08 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -171,8 +171,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
 	writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
 			&dma_p->busmode);
 
-	writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
-	writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
+	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
+		TXSECONDFRAME, &dma_p->opmode);
 
 	conf = FRAMEBURSTENABLE | DISABLERXOWN;
 
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index eee41d7..fbfc842 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -424,14 +424,12 @@ static void fec_reg_setup(struct fec_priv *fec)
 
 	/* Start with frame length = 1518, common for all modes. */
 	rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
-	if (fec->xcv_type == SEVENWIRE)
-		rcntrl |= FEC_RCNTRL_FCE;
-	else if (fec->xcv_type == RGMII)
+	if (fec->xcv_type != SEVENWIRE)		/* xMII modes */
+		rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
+	if (fec->xcv_type == RGMII)
 		rcntrl |= FEC_RCNTRL_RGMII;
 	else if (fec->xcv_type == RMII)
 		rcntrl |= FEC_RCNTRL_RMII;
-	else	/* MII mode */
-		rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
 
 	writel(rcntrl, &fec->eth->r_cntrl);
 }
@@ -510,7 +508,13 @@ static int fec_open(struct eth_device *edev)
 		fec_eth_phy_config(edev);
 	if (fec->phydev) {
 		/* Start up the PHY */
-		phy_startup(fec->phydev);
+		int ret = phy_startup(fec->phydev);
+
+		if (ret) {
+			printf("Could not initialize PHY %s\n",
+			       fec->phydev->dev->name);
+			return ret;
+		}
 		speed = fec->phydev->speed;
 	} else {
 		speed = _100BASET;
@@ -599,7 +603,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 
 	fec_reg_setup(fec);
 
-	if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
+	if (fec->xcv_type != SEVENWIRE)
 		fec_mii_setspeed(fec);
 
 	/*
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index f34f4db..2b616ad 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -363,6 +363,9 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
 {
 	struct fm_eth *fm_eth;
 	struct fsl_enet_mac *mac;
+#ifdef CONFIG_PHYLIB
+	int ret;
+#endif
 
 	fm_eth = (struct fm_eth *)dev->priv;
 	mac = fm_eth->mac;
@@ -384,7 +387,11 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
 	fmc_tx_port_graceful_stop_disable(fm_eth);
 
 #ifdef CONFIG_PHYLIB
-	phy_startup(fm_eth->phydev);
+	ret = phy_startup(fm_eth->phydev);
+	if (ret) {
+		printf("%s: Could not initialize\n", fm_eth->phydev->dev->name);
+		return ret;
+	}
 #else
 	fm_eth->phydev->speed = SPEED_1000;
 	fm_eth->phydev->link = 1;
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index e3043df..30f3264 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -35,6 +35,12 @@ static struct phy_driver KSZ804_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+#ifndef CONFIG_PHY_MICREL_KSZ9021
+/*
+ * I can't believe Micrel used the exact same part number
+ * for the KSZ9021
+ * Shame Micrel, Shame!!!!!
+ */
 static struct phy_driver KS8721_driver = {
 	.name = "Micrel KS8721BL",
 	.uid = 0x221610,
@@ -44,7 +50,9 @@ static struct phy_driver KS8721_driver = {
 	.startup = &genphy_startup,
 	.shutdown = &genphy_shutdown,
 };
+#endif
 
+#ifdef CONFIG_PHY_MICREL_KSZ9021
 /* ksz9021 PHY Registers */
 #define MII_KSZ9021_EXTENDED_CTRL	0x0b
 #define MII_KSZ9021_EXTENDED_DATAW	0x0c
@@ -127,12 +135,15 @@ static struct phy_driver ksz9021_driver = {
 	.startup = &ksz9021_startup,
 	.shutdown = &genphy_shutdown,
 };
+#endif
 
 int phy_micrel_init(void)
 {
 	phy_register(&KSZ804_driver);
-	phy_register(&KS8721_driver);
+#ifdef CONFIG_PHY_MICREL_KSZ9021
 	phy_register(&ksz9021_driver);
-
+#else
+	phy_register(&KS8721_driver);
+#endif
 	return 0;
 }
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 7d327f7..baef60f 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -723,10 +723,13 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 	return phydev;
 }
 
+/*
+ * Start the PHY.  Returns 0 on success, or a negative error code.
+ */
 int phy_startup(struct phy_device *phydev)
 {
 	if (phydev->drv->startup)
-		phydev->drv->startup(phydev);
+		return phydev->drv->startup(phydev);
 
 	return 0;
 }
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index bb57e4d..09af860 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -1,5 +1,5 @@
 /*
- * sh_eth.c - Driver for Renesas SH7763's ethernet controler.
+ * sh_eth.c - Driver for Renesas ethernet controler.
  *
  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
  * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
@@ -76,8 +76,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
 		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
 
 	/* Restart the transmitter if disabled */
-	if (!(inl(EDTRR(port)) & EDTRR_TRNS))
-		outl(EDTRR_TRNS, EDTRR(port));
+	if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
+		sh_eth_write(eth, EDTRR_TRNS, EDTRR);
 
 	/* Wait until packet is transmitted */
 	timeout = TIMEOUT_CNT;
@@ -129,25 +129,24 @@ int sh_eth_recv(struct eth_device *dev)
 	}
 
 	/* Restart the receiver if disabled */
-	if (!(inl(EDRRR(port)) & EDRRR_R))
-		outl(EDRRR_R, EDRRR(port));
+	if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
+		sh_eth_write(eth, EDRRR_R, EDRRR);
 
 	return len;
 }
 
 static int sh_eth_reset(struct sh_eth_dev *eth)
 {
-	int port = eth->port;
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	int ret = 0, i;
 
 	/* Start e-dmac transmitter and receiver */
-	outl(EDSR_ENALL, EDSR(port));
+	sh_eth_write(eth, EDSR_ENALL, EDSR);
 
 	/* Perform a software reset and wait for it to complete */
-	outl(EDMR_SRST, EDMR(port));
+	sh_eth_write(eth, EDMR_SRST, EDMR);
 	for (i = 0; i < TIMEOUT_CNT ; i++) {
-		if (!(inl(EDMR(port)) & EDMR_SRST))
+		if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
 			break;
 		udelay(1000);
 	}
@@ -159,9 +158,9 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
 
 	return ret;
 #else
-	outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
+	sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
 	udelay(3000);
-	outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
+	sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
 
 	return 0;
 #endif
@@ -207,11 +206,11 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 
 	/* Point the controller to the tx descriptor list. Must use physical
 	   addresses */
-	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
-	outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
-	outl(0x01, TDFFR(port));/* Last discriptor bit */
+	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
+#if defined(SH_ETH_TYPE_GETHER)
+	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
+	sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
+	sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
 #endif
 
 err:
@@ -275,11 +274,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 	cur_rx_desc->rd0 |= RD_RDLE;
 
 	/* Point the controller to the rx descriptor list */
-	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
-	outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
-	outl(RDFFR_RDLF, RDFFR(port));
+	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
+#if defined(SH_ETH_TYPE_GETHER)
+	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
+	sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
+	sh_eth_write(eth, RDFFR_RDLF, RDFFR);
 #endif
 
 	return ret;
@@ -364,49 +363,39 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	struct phy_device *phy;
 
 	/* Configure e-dmac registers */
-	outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
-	outl(0, EESIPR(port));
-	outl(0, TRSCER(port));
-	outl(0, TFTR(port));
-	outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
-	outl(RMCR_RST, RMCR(port));
-#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
-	outl(0, RPADIR(port));
+	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL,
+		     EDMR);
+	sh_eth_write(eth, 0, EESIPR);
+	sh_eth_write(eth, 0, TRSCER);
+	sh_eth_write(eth, 0, TFTR);
+	sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
+	sh_eth_write(eth, RMCR_RST, RMCR);
+#if defined(SH_ETH_TYPE_GETHER)
+	sh_eth_write(eth, 0, RPADIR);
 #endif
-	outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
+	sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 
 	/* Configure e-mac registers */
-#if defined(CONFIG_CPU_SH7757)
-	outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
-		ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
-#else
-	outl(0, ECSIPR(port));
-#endif
+	sh_eth_write(eth, 0, ECSIPR);
 
 	/* Set Mac address */
 	val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
 	    dev->enetaddr[2] << 8 | dev->enetaddr[3];
-	outl(val, MAHR(port));
+	sh_eth_write(eth, val, MAHR);
 
 	val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
-	outl(val, MALR(port));
-
-	outl(RFLR_RFL_MIN, RFLR(port));
-#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
-	outl(0, PIPR(port));
-#endif
-#if !defined(CONFIG_CPU_SH7724)
-	outl(APR_AP, APR(port));
-	outl(MPR_MP, MPR(port));
-#endif
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-	outl(TPAUSER_TPAUSE, TPAUSER(port));
-#elif defined(CONFIG_CPU_SH7757)
-	outl(TPAUSER_UNLIMITED, TPAUSER(port));
+	sh_eth_write(eth, val, MALR);
+
+	sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
+#if defined(SH_ETH_TYPE_GETHER)
+	sh_eth_write(eth, 0, PIPR);
+	sh_eth_write(eth, APR_AP, APR);
+	sh_eth_write(eth, MPR_MP, MPR);
+	sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
 #endif
 
 #if defined(CONFIG_CPU_SH7734)
-	outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port));
+	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 #endif
 	/* Configure phy */
 	ret = sh_eth_phy_config(eth);
@@ -415,42 +404,47 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 		goto err_phy_cfg;
 	}
 	phy = port_info->phydev;
-	phy_startup(phy);
+	ret = phy_startup(phy);
+	if (ret) {
+		printf(SHETHER_NAME ": phy startup failure\n");
+		return ret;
+	}
 
 	val = 0;
 
 	/* Set the transfer speed */
 	if (phy->speed == 100) {
 		printf(SHETHER_NAME ": 100Base/");
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-		outl(GECMR_100B, GECMR(port));
+#if defined(SH_ETH_TYPE_GETHER)
+		sh_eth_write(eth, GECMR_100B, GECMR);
 #elif defined(CONFIG_CPU_SH7757)
-		outl(1, RTRATE(port));
+		sh_eth_write(eth, 1, RTRATE);
 #elif defined(CONFIG_CPU_SH7724)
 		val = ECMR_RTM;
 #endif
 	} else if (phy->speed == 10) {
 		printf(SHETHER_NAME ": 10Base/");
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-		outl(GECMR_10B, GECMR(port));
+#if defined(SH_ETH_TYPE_GETHER)
+		sh_eth_write(eth, GECMR_10B, GECMR);
 #elif defined(CONFIG_CPU_SH7757)
-		outl(0, RTRATE(port));
+		sh_eth_write(eth, 0, RTRATE);
 #endif
 	}
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	else if (phy->speed == 1000) {
 		printf(SHETHER_NAME ": 1000Base/");
-		outl(GECMR_1000B, GECMR(port));
+		sh_eth_write(eth, GECMR_1000B, GECMR);
 	}
 #endif
 
 	/* Check if full duplex mode is supported by the phy */
 	if (phy->duplex) {
 		printf("Full\n");
-		outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
+		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
+			     ECMR);
 	} else {
 		printf("Half\n");
-		outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE),  ECMR(port));
+		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
 	}
 
 	return ret;
@@ -465,12 +459,12 @@ static void sh_eth_start(struct sh_eth_dev *eth)
 	 * Enable the e-dmac receiver only. The transmitter will be enabled when
 	 * we have something to transmit
 	 */
-	outl(EDRRR_R, EDRRR(eth->port));
+	sh_eth_write(eth, EDRRR_R, EDRRR);
 }
 
 static void sh_eth_stop(struct sh_eth_dev *eth)
 {
-	outl(~EDRRR_R, EDRRR(eth->port));
+	sh_eth_write(eth, ~EDRRR_R, EDRRR);
 }
 
 int sh_eth_init(struct eth_device *dev, bd_t *bd)
@@ -574,9 +568,8 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
-	outl(inl(PIR(port)) | PIR_MMD, PIR(port));
+	sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
 
 	return 0;
 }
@@ -584,9 +577,8 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
-	outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
+	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
 
 	return 0;
 }
@@ -594,12 +586,11 @@ static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
 	if (v)
-		outl(inl(PIR(port)) | PIR_MDO, PIR(port));
+		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
 	else
-		outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
+		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
 
 	return 0;
 }
@@ -607,9 +598,8 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
-	*v = (inl(PIR(port)) & PIR_MDI) >> 3;
+	*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
 
 	return 0;
 }
@@ -617,12 +607,11 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
 	if (v)
-		outl(inl(PIR(port)) | PIR_MDC, PIR(port));
+		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
 	else
-		outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
+		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
 
 	return 0;
 }
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 50f4b69..3703c55 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -97,143 +97,208 @@ struct sh_eth_dev {
 	struct sh_eth_info port_info[MAX_PORT_NUM];
 };
 
-/* Register Address */
-#ifdef CONFIG_CPU_SH7763
-#define BASE_IO_ADDR	0xfee00000
+/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
+enum {
+	/* E-DMAC registers */
+	EDSR = 0,
+	EDMR,
+	EDTRR,
+	EDRRR,
+	EESR,
+	EESIPR,
+	TDLAR,
+	TDFAR,
+	TDFXR,
+	TDFFR,
+	RDLAR,
+	RDFAR,
+	RDFXR,
+	RDFFR,
+	TRSCER,
+	RMFCR,
+	TFTR,
+	FDR,
+	RMCR,
+	EDOCR,
+	TFUCR,
+	RFOCR,
+	FCFTR,
+	RPADIR,
+	TRIMD,
+	RBWAR,
+	TBRAR,
+
+	/* Ether registers */
+	ECMR,
+	ECSR,
+	ECSIPR,
+	PIR,
+	PSR,
+	RDMLR,
+	PIPR,
+	RFLR,
+	IPGR,
+	APR,
+	MPR,
+	PFTCR,
+	PFRCR,
+	RFCR,
+	RFCF,
+	TPAUSER,
+	TPAUSECR,
+	BCFR,
+	BCFRR,
+	GECMR,
+	BCULR,
+	MAHR,
+	MALR,
+	TROCR,
+	CDCR,
+	LCCR,
+	CNDCR,
+	CEFCR,
+	FRECR,
+	TSFRCR,
+	TLFRCR,
+	CERCR,
+	CEECR,
+	MAFCR,
+	RTRATE,
+	CSMR,
+	RMII_MII,
+
+	/* This value must be written at last. */
+	SH_ETH_MAX_REGISTER_OFFSET,
+};
 
-#define EDSR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0000)
-
-#define TDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0010)
-#define TDFAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0014)
-#define TDFXR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0018)
-#define TDFFR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x001c)
-
-#define RDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0030)
-#define RDFAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0034)
-#define RDFXR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0038)
-#define RDFFR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x003c)
-
-#define EDMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0400)
-#define EDTRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0408)
-#define EDRRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0410)
-#define EESR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0428)
-#define EESIPR(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0430)
-#define TRSCER(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0438)
-#define TFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0448)
-#define FDR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0450)
-#define RMCR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0458)
-#define RPADIR(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0460)
-#define FCFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0468)
-#define ECMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0500)
-#define RFLR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0508)
-#define ECSIPR(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0518)
-#define PIR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0520)
-#define PIPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x052c)
-#define APR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0554)
-#define MPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0558)
-#define TPAUSER(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0564)
-#define GECMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
-#define MALR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
-#define MAHR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
+static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
+	[EDSR]	= 0x0000,
+	[EDMR]	= 0x0400,
+	[EDTRR]	= 0x0408,
+	[EDRRR]	= 0x0410,
+	[EESR]	= 0x0428,
+	[EESIPR]	= 0x0430,
+	[TDLAR]	= 0x0010,
+	[TDFAR]	= 0x0014,
+	[TDFXR]	= 0x0018,
+	[TDFFR]	= 0x001c,
+	[RDLAR]	= 0x0030,
+	[RDFAR]	= 0x0034,
+	[RDFXR]	= 0x0038,
+	[RDFFR]	= 0x003c,
+	[TRSCER]	= 0x0438,
+	[RMFCR]	= 0x0440,
+	[TFTR]	= 0x0448,
+	[FDR]	= 0x0450,
+	[RMCR]	= 0x0458,
+	[RPADIR]	= 0x0460,
+	[FCFTR]	= 0x0468,
+	[CSMR] = 0x04E4,
+
+	[ECMR]	= 0x0500,
+	[ECSR]	= 0x0510,
+	[ECSIPR]	= 0x0518,
+	[PIR]	= 0x0520,
+	[PSR]	= 0x0528,
+	[PIPR]	= 0x052c,
+	[RFLR]	= 0x0508,
+	[APR]	= 0x0554,
+	[MPR]	= 0x0558,
+	[PFTCR]	= 0x055c,
+	[PFRCR]	= 0x0560,
+	[TPAUSER]	= 0x0564,
+	[GECMR]	= 0x05b0,
+	[BCULR]	= 0x05b4,
+	[MAHR]	= 0x05c0,
+	[MALR]	= 0x05c8,
+	[TROCR]	= 0x0700,
+	[CDCR]	= 0x0708,
+	[LCCR]	= 0x0710,
+	[CEFCR]	= 0x0740,
+	[FRECR]	= 0x0748,
+	[TSFRCR]	= 0x0750,
+	[TLFRCR]	= 0x0758,
+	[RFCR]	= 0x0760,
+	[CERCR]	= 0x0768,
+	[CEECR]	= 0x0770,
+	[MAFCR]	= 0x0778,
+	[RMII_MII] =  0x0790,
+};
 
+static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
+	[ECMR]	= 0x0100,
+	[RFLR]	= 0x0108,
+	[ECSR]	= 0x0110,
+	[ECSIPR]	= 0x0118,
+	[PIR]	= 0x0120,
+	[PSR]	= 0x0128,
+	[RDMLR]	= 0x0140,
+	[IPGR]	= 0x0150,
+	[APR]	= 0x0154,
+	[MPR]	= 0x0158,
+	[TPAUSER]	= 0x0164,
+	[RFCF]	= 0x0160,
+	[TPAUSECR]	= 0x0168,
+	[BCFRR]	= 0x016c,
+	[MAHR]	= 0x01c0,
+	[MALR]	= 0x01c8,
+	[TROCR]	= 0x01d0,
+	[CDCR]	= 0x01d4,
+	[LCCR]	= 0x01d8,
+	[CNDCR]	= 0x01dc,
+	[CEFCR]	= 0x01e4,
+	[FRECR]	= 0x01e8,
+	[TSFRCR]	= 0x01ec,
+	[TLFRCR]	= 0x01f0,
+	[RFCR]	= 0x01f4,
+	[MAFCR]	= 0x01f8,
+	[RTRATE]	= 0x01fc,
+
+	[EDMR]	= 0x0000,
+	[EDTRR]	= 0x0008,
+	[EDRRR]	= 0x0010,
+	[TDLAR]	= 0x0018,
+	[RDLAR]	= 0x0020,
+	[EESR]	= 0x0028,
+	[EESIPR]	= 0x0030,
+	[TRSCER]	= 0x0038,
+	[RMFCR]	= 0x0040,
+	[TFTR]	= 0x0048,
+	[FDR]	= 0x0050,
+	[RMCR]	= 0x0058,
+	[TFUCR]	= 0x0064,
+	[RFOCR]	= 0x0068,
+	[FCFTR]	= 0x0070,
+	[RPADIR]	= 0x0078,
+	[TRIMD]	= 0x007c,
+	[RBWAR]	= 0x00c8,
+	[RDFAR]	= 0x00cc,
+	[TBRAR]	= 0x00d4,
+	[TDFAR]	= 0x00d8,
+};
+
+/* Register Address */
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR	0xfee00000
 #elif defined(CONFIG_CPU_SH7757)
+#if defined(CONFIG_SH_ETHER_USE_GETHER)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR	0xfee00000
+#else
+#define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR	0xfef00000
-
-#define TDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0018)
-#define RDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0020)
-
-#define EDMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0000)
-#define EDTRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0008)
-#define EDRRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0010)
-#define EESR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0028)
-#define EESIPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0030)
-#define TRSCER(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0038)
-#define TFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0048)
-#define FDR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0050)
-#define RMCR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0058)
-#define FCFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0070)
-#define ECMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0100)
-#define RFLR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0108)
-#define ECSIPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0118)
-#define PIR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0120)
-#define APR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0154)
-#define MPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0158)
-#define TPAUSER(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0164)
-#define MAHR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
-#define MALR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
-#define RTRATE(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
-
+#endif
 #elif defined(CONFIG_CPU_SH7724)
+#define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR	0xA4600000
-
-#define TDLAR(port)		(BASE_IO_ADDR + 0x0018)
-#define RDLAR(port)		(BASE_IO_ADDR + 0x0020)
-
-#define EDMR(port)		(BASE_IO_ADDR + 0x0000)
-#define EDTRR(port)		(BASE_IO_ADDR + 0x0008)
-#define EDRRR(port)		(BASE_IO_ADDR + 0x0010)
-#define EESR(port)		(BASE_IO_ADDR + 0x0028)
-#define EESIPR(port)	(BASE_IO_ADDR + 0x0030)
-#define TRSCER(port)	(BASE_IO_ADDR + 0x0038)
-#define TFTR(port)		(BASE_IO_ADDR + 0x0048)
-#define FDR(port)		(BASE_IO_ADDR + 0x0050)
-#define RMCR(port)		(BASE_IO_ADDR + 0x0058)
-#define FCFTR(port)		(BASE_IO_ADDR + 0x0070)
-#define ECMR(port)		(BASE_IO_ADDR + 0x0100)
-#define RFLR(port)		(BASE_IO_ADDR + 0x0108)
-#define ECSIPR(port)	(BASE_IO_ADDR + 0x0118)
-#define PIR(port)		(BASE_IO_ADDR + 0x0120)
-#define APR(port)		(BASE_IO_ADDR + 0x0154)
-#define MPR(port)		(BASE_IO_ADDR + 0x0158)
-#define TPAUSER(port)	(BASE_IO_ADDR + 0x0164)
-#define MAHR(port)		(BASE_IO_ADDR + 0x01c0)
-#define MALR(port)		(BASE_IO_ADDR + 0x01c8)
-
-#elif defined(CONFIG_CPU_SH7734)
-#define BASE_IO_ADDR	0xFEE00000
-
-#define EDSR(port)		(BASE_IO_ADDR)
-
-#define TDLAR(port)		(BASE_IO_ADDR + 0x0010)
-#define TDFAR(port)		(BASE_IO_ADDR + 0x0014)
-#define TDFXR(port)		(BASE_IO_ADDR + 0x0018)
-#define TDFFR(port)		(BASE_IO_ADDR + 0x001c)
-#define RDLAR(port)		(BASE_IO_ADDR + 0x0030)
-#define RDFAR(port)		(BASE_IO_ADDR + 0x0034)
-#define RDFXR(port)		(BASE_IO_ADDR + 0x0038)
-#define RDFFR(port)		(BASE_IO_ADDR + 0x003c)
-
-#define EDMR(port)		(BASE_IO_ADDR + 0x0400)
-#define EDTRR(port)		(BASE_IO_ADDR + 0x0408)
-#define EDRRR(port)		(BASE_IO_ADDR + 0x0410)
-#define EESR(port)		(BASE_IO_ADDR + 0x0428)
-#define EESIPR(port)	(BASE_IO_ADDR + 0x0430)
-#define TRSCER(port)	(BASE_IO_ADDR + 0x0438)
-#define TFTR(port)		(BASE_IO_ADDR + 0x0448)
-#define FDR(port)		(BASE_IO_ADDR + 0x0450)
-#define RMCR(port)		(BASE_IO_ADDR + 0x0458)
-#define RPADIR(port)	(BASE_IO_ADDR + 0x0460)
-#define FCFTR(port)		(BASE_IO_ADDR + 0x0468)
-#define ECMR(port)		(BASE_IO_ADDR + 0x0500)
-#define RFLR(port)		(BASE_IO_ADDR + 0x0508)
-#define ECSIPR(port)	(BASE_IO_ADDR + 0x0518)
-#define PIR(port)		(BASE_IO_ADDR + 0x0520)
-#define PIPR(port)		(BASE_IO_ADDR + 0x052c)
-#define APR(port)		(BASE_IO_ADDR + 0x0554)
-#define MPR(port)		(BASE_IO_ADDR + 0x0558)
-#define TPAUSER(port)	(BASE_IO_ADDR + 0x0564)
-#define GECMR(port)		(BASE_IO_ADDR + 0x05b0)
-#define MAHR(port)		(BASE_IO_ADDR + 0x05C0)
-#define MALR(port)		(BASE_IO_ADDR + 0x05C8)
-#define RMII_MII(port)  (BASE_IO_ADDR + 0x0790)
-
 #endif
 
 /*
  * Register's bits
  * Copy from Linux driver source code
  */
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 /* EDSR */
 enum EDSR_BIT {
 	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
@@ -244,15 +309,15 @@ enum EDSR_BIT {
 /* EDMR */
 enum DMAC_M_BIT {
 	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	EDMR_SRST	= 0x03, /* Receive/Send reset */
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
-#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724)
+#elif defined(SH_ETH_TYPE_ETHER)
 	EDMR_SRST	= 0x01,
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
-#else /* CONFIG_CPU_SH7763 */
+#else
 	EDMR_SRST = 0x01,
 #endif
 };
@@ -262,7 +327,7 @@ enum DMAC_M_BIT {
 
 /* EDTRR */
 enum DMAC_T_BIT {
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	EDTRR_TRNS = 0x03,
 #else
 	EDTRR_TRNS = 0x01,
@@ -271,7 +336,11 @@ enum DMAC_T_BIT {
 
 /* GECMR */
 enum GECMR_BIT {
+#if defined(CONFIG_CPU_SH7757)
+	GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
+#else
 	GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
+#endif
 };
 
 /* EDRRR*/
@@ -302,7 +371,7 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 /* EESR */
 enum EESR_BIT {
 
-#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	EESR_TWB  = 0x40000000,
 #else
 	EESR_TWB  = 0xC0000000,
@@ -312,14 +381,14 @@ enum EESR_BIT {
 #endif
 	EESR_TABT = 0x04000000,
 	EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
-#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	EESR_ADE  = 0x00800000,
 #endif
 	EESR_ECI  = 0x00400000,
 	EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 	EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 	EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
-#if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	EESR_CND  = 0x00000800,
 #endif
 	EESR_DLC  = 0x00000400,
@@ -331,7 +400,7 @@ enum EESR_BIT {
 };
 
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 # define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 		| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
@@ -391,8 +460,7 @@ enum FCFTR_BIT {
 
 /* Transfer descriptor bit */
 enum TD_STS_BIT {
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
-		|| defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER)
 	TD_TACT = 0x80000000,
 #else
 	TD_TACT = 0x7fffffff,
@@ -408,7 +476,7 @@ enum TD_STS_BIT {
 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 /* ECMR */
 enum FELIC_MODE_BIT {
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
 	ECMR_RZPF = 0x00100000,
 #endif
@@ -423,12 +491,10 @@ enum FELIC_MODE_BIT {
 
 };
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 #define ECMR_CHG_DM	(ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
 						ECMR_TXF | ECMR_MCT)
-#elif CONFIG_CPU_SH7757
-#define ECMR_CHG_DM	(ECMR_ZPF)
-#elif CONFIG_CPU_SH7724
+#elif defined(SH_ETH_TYPE_ETHER)
 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
 #else
 #define ECMR_CHG_DM	(ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
@@ -436,14 +502,14 @@ enum FELIC_MODE_BIT {
 
 /* ECSR */
 enum ECSR_STATUS_BIT {
-#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 #endif
 	ECSR_LCHNG = 0x04,
 	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 };
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 #else
 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
@@ -452,10 +518,10 @@ enum ECSR_STATUS_BIT {
 
 /* ECSIPR */
 enum ECSIPR_STATUS_MASK_BIT {
-#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	ECSIPR_BRCRXIP = 0x20,
 	ECSIPR_PSRTOIP = 0x10,
-#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#elif defined(SH_ETY_TYPE_GETHER)
 	ECSIPR_PSRTOIP = 0x10,
 	ECSIPR_PHYIP = 0x08,
 #endif
@@ -464,7 +530,7 @@ enum ECSIPR_STATUS_MASK_BIT {
 	ECSIPR_ICDIP = 0x01,
 };
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 #else
 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
@@ -473,20 +539,12 @@ enum ECSIPR_STATUS_MASK_BIT {
 
 /* APR */
 enum APR_BIT {
-#ifdef CONFIG_CPU_SH7757
-	APR_AP = 0x00000001,
-#else
 	APR_AP = 0x00000004,
-#endif
 };
 
 /* MPR */
 enum MPR_BIT {
-#ifdef CONFIG_CPU_SH7757
-	MPR_MP = 0x00000001,
-#else
 	MPR_MP = 0x00000006,
-#endif
 };
 
 /* TRSCER */
@@ -503,7 +561,7 @@ enum RPADIR_BIT {
 	RPADIR_PADR = 0x0003f,
 };
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 # define RPADIR_INIT (0x00)
 #else
 # define RPADIR_INIT (RPADIR_PADS1)
@@ -513,3 +571,28 @@ enum RPADIR_BIT {
 enum FIFO_SIZE_BIT {
 	FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 };
+
+static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
+					    int enum_index)
+{
+#if defined(SH_ETH_TYPE_GETHER)
+	const u16 *reg_offset = sh_eth_offset_gigabit;
+#elif defined(SH_ETH_TYPE_ETHER)
+	const u16 *reg_offset = sh_eth_offset_fast_sh4;
+#else
+#error
+#endif
+	return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
+}
+
+static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
+				int enum_index)
+{
+	outl(data, sh_eth_reg_addr(eth, enum_index));
+}
+
+static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
+					int enum_index)
+{
+	return inl(sh_eth_reg_addr(eth, enum_index));
+}
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 3c1c8f0..f5e314b 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -480,6 +480,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
 	int i;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
 	tsec_t *regs = priv->regs;
+	int ret;
 
 	/* Make sure the controller is stopped */
 	tsec_halt(dev);
@@ -511,7 +512,12 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
 	startup_tsec(dev);
 
 	/* Start up the PHY */
-	phy_startup(priv->phydev);
+	ret = phy_startup(priv->phydev);
+	if (ret) {
+		printf("Could not initialize PHY %s\n",
+		       priv->phydev->dev->name);
+		return ret;
+	}
 
 	adjust_link(priv, priv->phydev);
 
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 7854a04..d777144 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -272,7 +272,11 @@ static int setup_phy(struct eth_device *dev)
 	phydev->advertising = phydev->supported;
 	priv->phydev = phydev;
 	phy_config(phydev);
-	phy_startup(phydev);
+	if (phy_startup(phydev)) {
+		printf("axiemac: could not initialize PHY %s\n",
+		       phydev->dev->name);
+		return 0;
+	}
 
 	switch (phydev->speed) {
 	case 1000:
diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c
index 27dafc1..b67153b 100644
--- a/drivers/net/xilinx_ll_temac.c
+++ b/drivers/net/xilinx_ll_temac.c
@@ -232,6 +232,7 @@ static void ll_temac_halt(struct eth_device *dev)
 static int ll_temac_init(struct eth_device *dev, bd_t *bis)
 {
 	struct ll_temac *ll_temac = dev->priv;
+	int ret;
 
 	printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n",
 		dev->name, dev->index, dev->iobase);
@@ -240,7 +241,12 @@ static int ll_temac_init(struct eth_device *dev, bd_t *bis)
 		return -1;
 
 	/* Start up the PHY */
-	phy_startup(ll_temac->phydev);
+	ret = phy_startup(ll_temac->phydev);
+	if (ret) {
+		printf("%s: Could not initialize PHY %s\n",
+		       dev->name, ll_temac->phydev->dev->name);
+		return ret;
+	}
 
 	if (!ll_temac_adjust_link(dev)) {
 		ll_temac_halt(dev);