Merge git://www.denx.de/git/u-boot into uboot

10 files changed, 1396 insertions, 366 deletions

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b9723fa..320dc3e 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -27,6 +27,7 @@ LIB 	:= $(obj)libnet.a
 
 COBJS-y += 3c589.o
 COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o
+COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
 COBJS-y += cs8900.o
 COBJS-y += dc2114x.o
 COBJS-y += dm9000x.o
@@ -40,7 +41,7 @@ COBJS-y += lan91c96.o
 COBJS-y += macb.o
 COBJS-y += mcffec.o
 COBJS-y += natsemi.o
-COBJS-y += ne2000.o
+COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o
 COBJS-y += netarm_eth.o
 COBJS-y += netconsole.o
 COBJS-y += ns7520_eth.o
@@ -57,6 +58,7 @@ COBJS-y += tigon3.o
 COBJS-y += tsec.o
 COBJS-y += tsi108_eth.o
 COBJS-y += uli526x.o
+COBJS-y += vsc7385.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/net/ax88796.h b/drivers/net/ax88796.h
new file mode 100644
index 0000000..069ae80
--- /dev/null
+++ b/drivers/net/ax88796.h
@@ -0,0 +1,217 @@
+/*
+ * AX88796L(NE2000) support
+ *
+ * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __DRIVERS_AX88796L_H__
+#define __DRIVERS_AX88796L_H__
+
+#define DP_DATA     (0x10 << 1)
+#define START_PG    0x40    /* First page of TX buffer */
+#define START_PG2   0x48
+#define STOP_PG     0x80    /* Last page +1 of RX ring */
+#define TX_PAGES    12
+#define RX_START    (START_PG+TX_PAGES)
+#define RX_END      STOP_PG
+
+#define AX88796L_BASE_ADDRESS	CONFIG_DRIVER_NE2000_BASE
+#define AX88796L_BYTE_ACCESS    0x00001000
+#define AX88796L_OFFSET         0x00000400
+#define AX88796L_ADDRESS_BYTE   AX88796L_BASE_ADDRESS + \
+		AX88796L_BYTE_ACCESS + AX88796L_OFFSET
+#define AX88796L_REG_MEMR       AX88796L_ADDRESS_BYTE + (0x14<<1)
+#define AX88796L_REG_CR         AX88796L_ADDRESS_BYTE + (0x00<<1)
+
+#define AX88796L_CR		(*(vu_short *)(AX88796L_REG_CR))
+#define AX88796L_MEMR	(*(vu_short *)(AX88796L_REG_MEMR))
+
+#define EECS_HIGH		(AX88796L_MEMR |= 0x10)
+#define EECS_LOW		(AX88796L_MEMR &= 0xef)
+#define EECLK_HIGH		(AX88796L_MEMR |= 0x80)
+#define EECLK_LOW		(AX88796L_MEMR &= 0x7f)
+#define EEDI_HIGH		(AX88796L_MEMR |= 0x20)
+#define EEDI_LOW		(AX88796L_MEMR &= 0xdf)
+#define EEDO			((AX88796L_MEMR & 0x40)>>6)
+
+#define PAGE0_SET		(AX88796L_CR &= 0x3f)
+#define PAGE1_SET		(AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40)
+
+#define BIT_DUMMY		0
+#define MAC_EEP_READ	1
+#define MAC_EEP_WRITE	2
+#define MAC_EEP_ERACE	3
+#define MAC_EEP_EWEN	4
+#define MAC_EEP_EWDS	5
+
+/* R7780MP Specific code */
+#if defined(CONFIG_R7780MP)
+#define ISA_OFFSET  0x1400
+#define DP_IN(_b_, _o_, _d_)  (_d_) = \
+	*( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET))
+#define DP_OUT(_b_, _o_, _d_) \
+	*((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_)
+#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
+#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
+#else
+/* Please change for your target boards */
+#define ISA_OFFSET  0x0000
+#define DP_IN(_b_, _o_, _d_)  (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
+#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
+#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
+#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
+#endif
+
+
+/*
+ * Set 1 bit data
+ */
+static void ax88796_bitset(u32 bit)
+{
+	/* DATA1 */
+	if( bit )
+		EEDI_HIGH;
+	else
+		EEDI_LOW;
+
+	EECLK_LOW;
+	udelay(1000);
+	EECLK_HIGH;
+	udelay(1000);
+	EEDI_LOW;
+}
+
+/*
+ * Get 1 bit data
+ */
+static u8 ax88796_bitget(void)
+{
+	u8 bit;
+
+	EECLK_LOW;
+	udelay(1000);
+	/* DATA */
+	bit = EEDO;
+	EECLK_HIGH;
+	udelay(1000);
+
+	return bit;
+}
+
+/*
+ * Send COMMAND to EEPROM
+ */
+static void ax88796_eep_cmd(u8 cmd)
+{
+	ax88796_bitset(BIT_DUMMY);
+	switch(cmd){
+		case MAC_EEP_READ:
+			ax88796_bitset(1);
+			ax88796_bitset(1);
+			ax88796_bitset(0);
+			break;
+
+		case MAC_EEP_WRITE:
+			ax88796_bitset(1);
+			ax88796_bitset(0);
+			ax88796_bitset(1);
+			break;
+
+		case MAC_EEP_ERACE:
+			ax88796_bitset(1);
+			ax88796_bitset(1);
+			ax88796_bitset(1);
+			break;
+
+		case MAC_EEP_EWEN:
+			ax88796_bitset(1);
+			ax88796_bitset(0);
+			ax88796_bitset(0);
+			break;
+
+		case MAC_EEP_EWDS:
+			ax88796_bitset(1);
+			ax88796_bitset(0);
+			ax88796_bitset(0);
+			break;
+		default:
+			break;
+	}
+}
+
+static void ax88796_eep_setaddr(u16 addr)
+{
+	int i ;
+	for( i = 7 ; i >= 0 ; i-- )
+		ax88796_bitset(addr & (1 << i));
+}
+
+/*
+ * Get data from EEPROM
+ */
+static u16 ax88796_eep_getdata(void)
+{
+	ushort data = 0;
+	int i;
+
+	ax88796_bitget();	/* DUMMY */
+	for( i = 0 ; i < 16 ; i++ ){
+		data <<= 1;
+		data |= ax88796_bitget();
+	}
+	return data;
+}
+
+static void ax88796_mac_read(u8 *buff)
+{
+	int i ;
+	u16 data, addr = 0;
+
+	for( i = 0 ; i < 3; i++ )
+	{
+		EECS_HIGH;
+		EEDI_LOW;
+		udelay(1000);
+		/* READ COMMAND */
+		ax88796_eep_cmd(MAC_EEP_READ);
+		/* ADDRESS */
+		ax88796_eep_setaddr(addr++);
+		/* GET DATA */
+		data = ax88796_eep_getdata();
+		*buff++ = (uchar)(data & 0xff);
+		*buff++ = (uchar)((data >> 8) & 0xff);
+		EECLK_LOW;
+		EEDI_LOW;
+		EECS_LOW;
+	}
+}
+
+int get_prom(u8* mac_addr)
+{
+	u8 prom[32];
+	int i;
+
+	ax88796_mac_read(prom);
+	for (i = 0; i < 6; i++){
+		mac_addr[i] = prom[i];
+	}
+	return 1;
+}
+
+#endif /* __DRIVERS_AX88796L_H__ */
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
new file mode 100644
index 0000000..afe122a
--- /dev/null
+++ b/drivers/net/bfin_mac.c
@@ -0,0 +1,523 @@
+/*
+ * Driver for Blackfin On-Chip MAC device
+ *
+ * Copyright (c) 2005-2008 Analog Device, Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+#include <command.h>
+#include <malloc.h>
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/emac.h>
+#include <asm/mach-common/bits/pll.h>
+
+#include "bfin_mac.h"
+
+#ifdef CONFIG_POST
+#include <post.h>
+#endif
+
+#undef DEBUG_ETHERNET
+
+#ifdef DEBUG_ETHERNET
+#define DEBUGF(fmt, args...) printf(fmt, ##args)
+#else
+#define DEBUGF(fmt, args...)
+#endif
+
+#define RXBUF_BASE_ADDR		0xFF900000
+#define TXBUF_BASE_ADDR		0xFF800000
+#define TX_BUF_CNT		1
+
+#define TOUT_LOOP 		1000000
+
+ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
+ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
+static u16 txIdx;		/* index of the current RX buffer */
+static u16 rxIdx;		/* index of the current TX buffer */
+
+u16 PHYregs[NO_PHY_REGS];	/* u16 PHYADDR; */
+
+/* DMAx_CONFIG values at DMA Restart */
+const ADI_DMA_CONFIG_REG rxdmacfg = {
+	.b_DMA_EN  = 1,	/* enabled */
+	.b_WNR     = 1,	/* write to memory */
+	.b_WDSIZE  = 2,	/* wordsize is 32 bits */
+	.b_DMA2D   = 0,
+	.b_RESTART = 0,
+	.b_DI_SEL  = 0,
+	.b_DI_EN   = 0,	/* no interrupt */
+	.b_NDSIZE  = 5,	/* 5 half words is desc size */
+	.b_FLOW    = 7	/* large desc flow */
+};
+
+const ADI_DMA_CONFIG_REG txdmacfg = {
+	.b_DMA_EN  = 1,	/* enabled */
+	.b_WNR     = 0,	/* read from memory */
+	.b_WDSIZE  = 2,	/* wordsize is 32 bits */
+	.b_DMA2D   = 0,
+	.b_RESTART = 0,
+	.b_DI_SEL  = 0,
+	.b_DI_EN   = 0,	/* no interrupt */
+	.b_NDSIZE  = 5,	/* 5 half words is desc size */
+	.b_FLOW    = 7	/* large desc flow */
+};
+
+int bfin_EMAC_initialize(bd_t *bis)
+{
+	struct eth_device *dev;
+	dev = (struct eth_device *)malloc(sizeof(*dev));
+	if (dev == NULL)
+		hang();
+
+	memset(dev, 0, sizeof(*dev));
+	sprintf(dev->name, "Blackfin EMAC");
+
+	dev->iobase = 0;
+	dev->priv = 0;
+	dev->init = bfin_EMAC_init;
+	dev->halt = bfin_EMAC_halt;
+	dev->send = bfin_EMAC_send;
+	dev->recv = bfin_EMAC_recv;
+
+	eth_register(dev);
+
+	return 1;
+}
+
+static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	int i;
+	int result = 0;
+	unsigned int *buf;
+	buf = (unsigned int *)packet;
+
+	if (length <= 0) {
+		printf("Ethernet: bad packet size: %d\n", length);
+		goto out;
+	}
+
+	if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
+		printf("Ethernet: tx DMA error\n");
+		goto out;
+	}
+
+	for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
+		if (i > TOUT_LOOP) {
+			puts("Ethernet: tx time out\n");
+			goto out;
+		}
+	}
+	txbuf[txIdx]->FrmData->NoBytes = length;
+	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
+	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
+	*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
+	*pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
+	*pEMAC_OPMODE |= TE;
+
+	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
+		if (i > TOUT_LOOP) {
+			puts("Ethernet: tx error\n");
+			goto out;
+		}
+	}
+	result = txbuf[txIdx]->StatusWord;
+	txbuf[txIdx]->StatusWord = 0;
+	if ((txIdx + 1) >= TX_BUF_CNT)
+		txIdx = 0;
+	else
+		txIdx++;
+ out:
+	DEBUGF("BFIN EMAC send: length = %d\n", length);
+	return result;
+}
+
+static int bfin_EMAC_recv(struct eth_device *dev)
+{
+	int length = 0;
+
+	for (;;) {
+		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
+			length = -1;
+			break;
+		}
+		if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
+			printf("Ethernet: rx dma overrun\n");
+			break;
+		}
+		if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
+			printf("Ethernet: rx error\n");
+			break;
+		}
+		length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
+		if (length <= 4) {
+			printf("Ethernet: bad frame\n");
+			break;
+		}
+		NetRxPackets[rxIdx] =
+		    (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
+		NetReceive(NetRxPackets[rxIdx], length - 4);
+		*pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
+		rxbuf[rxIdx]->StatusWord = 0x00000000;
+		if ((rxIdx + 1) >= PKTBUFSRX)
+			rxIdx = 0;
+		else
+			rxIdx++;
+	}
+
+	return length;
+}
+
+/**************************************************************
+ *
+ * Ethernet Initialization Routine
+ *
+ *************************************************************/
+
+static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
+{
+	u32 opmode;
+	int dat;
+	int i;
+	DEBUGF("Eth_init: ......\n");
+
+	txIdx = 0;
+	rxIdx = 0;
+
+/* Initialize System Register */
+	if (SetupSystemRegs(&dat) < 0)
+		return -1;
+
+/* Initialize EMAC address */
+	bfin_EMAC_setup_addr(bd);
+
+/* Initialize TX and RX buffer */
+	for (i = 0; i < PKTBUFSRX; i++) {
+		rxbuf[i] = SetupRxBuffer(i);
+		if (i > 0) {
+			rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
+			    &(rxbuf[i]->Dma[0]);
+			if (i == (PKTBUFSRX - 1))
+				rxbuf[i]->Dma[1].NEXT_DESC_PTR =
+				    &(rxbuf[0]->Dma[0]);
+		}
+	}
+	for (i = 0; i < TX_BUF_CNT; i++) {
+		txbuf[i] = SetupTxBuffer(i);
+		if (i > 0) {
+			txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
+			    &(txbuf[i]->Dma[0]);
+			if (i == (TX_BUF_CNT - 1))
+				txbuf[i]->Dma[1].NEXT_DESC_PTR =
+				    &(txbuf[0]->Dma[0]);
+		}
+	}
+
+	/* Set RX DMA */
+	*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
+	*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
+
+	/* Wait MII done */
+	PollMdcDone();
+
+	/* We enable only RX here */
+	/* ASTP   : Enable Automatic Pad Stripping
+	   PR     : Promiscuous Mode for test
+	   PSF    : Receive frames with total length less than 64 bytes.
+	   FDMODE : Full Duplex Mode
+	   LB	  : Internal Loopback for test
+	   RE     : Receiver Enable */
+	if (dat == FDMODE)
+		opmode = ASTP | FDMODE | PSF;
+	else
+		opmode = ASTP | PSF;
+	opmode |= RE;
+#ifdef CONFIG_BFIN_MAC_RMII
+	opmode |= TE | RMII;
+#endif
+	/* Turn on the EMAC */
+	*pEMAC_OPMODE = opmode;
+	return 0;
+}
+
+static void bfin_EMAC_halt(struct eth_device *dev)
+{
+	DEBUGF("Eth_halt: ......\n");
+	/* Turn off the EMAC */
+	*pEMAC_OPMODE = 0x00000000;
+	/* Turn off the EMAC RX DMA */
+	*pDMA1_CONFIG = 0x0000;
+	*pDMA2_CONFIG = 0x0000;
+
+}
+
+void bfin_EMAC_setup_addr(bd_t *bd)
+{
+	*pEMAC_ADDRLO =
+		bd->bi_enetaddr[0] |
+		bd->bi_enetaddr[1] << 8 |
+		bd->bi_enetaddr[2] << 16 |
+		bd->bi_enetaddr[3] << 24;
+	*pEMAC_ADDRHI =
+		bd->bi_enetaddr[4] |
+		bd->bi_enetaddr[5] << 8;
+}
+
+static void PollMdcDone(void)
+{
+	/* poll the STABUSY bit */
+	while (*pEMAC_STAADD & STABUSY) ;
+}
+
+static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
+{
+	PollMdcDone();
+
+	*pEMAC_STADAT = Data;
+
+	*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
+	    STAOP | STAIE | STABUSY;
+}
+
+/*********************************************************************************
+ *		Read an off-chip register in a PHY through the MDC/MDIO port     *
+ *********************************************************************************/
+static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
+{
+	u16 Data;
+
+	PollMdcDone();
+
+	*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
+	    STAIE | STABUSY;
+
+	PollMdcDone();
+
+	Data = (u16) * pEMAC_STADAT;
+
+	PHYregs[RegAddr] = Data;	/* save shadow copy */
+
+	return Data;
+}
+
+#if 0 /* dead code ? */
+static void SoftResetPHY(void)
+{
+	u16 phydat;
+	/* set the reset bit */
+	WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
+	/* and clear it again */
+	WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
+	do {
+		/* poll until reset is complete */
+		phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
+	} while ((phydat & PHY_RESET) != 0);
+}
+#endif
+
+static int SetupSystemRegs(int *opmode)
+{
+	u16 sysctl, phydat;
+	int count = 0;
+	/* Enable PHY output */
+	*pVR_CTL |= CLKBUFOE;
+	/* Set all the pins to peripheral mode */
+
+#ifndef CONFIG_BFIN_MAC_RMII
+	*pPORTH_FER = 0xFFFF;
+#ifdef __ADSPBF52x__
+	*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
+#endif
+#else
+#if defined(__ADSPBF536__) || defined(__ADSPBF537__)
+	*pPORTH_FER = 0xC373;
+#endif
+#ifdef __ADSPBF52x__
+	*pPORTH_FER = 0x01FF;
+	*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
+#endif
+#endif
+	/* MDC  = 2.5 MHz */
+	sysctl = SET_MDCDIV(24);
+	/* Odd word alignment for Receive Frame DMA word */
+	/* Configure checksum support and rcve frame word alignment */
+	sysctl |= RXDWA | RXCKS;
+	*pEMAC_SYSCTL = sysctl;
+	/* auto negotiation on  */
+	/* full duplex */
+	/* 100 Mbps */
+	phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
+	WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
+	do {
+		udelay(1000);
+		phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
+		if (count > 3000) {
+			printf
+			    ("Link is down, please check your network connection\n");
+			return -1;
+		}
+		count++;
+	} while (!(phydat & 0x0004));
+
+	phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
+
+	if ((phydat & 0x0100) || (phydat & 0x0040))
+		*opmode = FDMODE;
+	else
+		*opmode = 0;
+
+	*pEMAC_MMC_CTL = RSTC | CROLL;
+
+	/* Initialize the TX DMA channel registers */
+	*pDMA2_X_COUNT = 0;
+	*pDMA2_X_MODIFY = 4;
+	*pDMA2_Y_COUNT = 0;
+	*pDMA2_Y_MODIFY = 0;
+
+	/* Initialize the RX DMA channel registers */
+	*pDMA1_X_COUNT = 0;
+	*pDMA1_X_MODIFY = 4;
+	*pDMA1_Y_COUNT = 0;
+	*pDMA1_Y_MODIFY = 0;
+	return 0;
+}
+
+ADI_ETHER_BUFFER *SetupRxBuffer(int no)
+{
+	ADI_ETHER_FRAME_BUFFER *frmbuf;
+	ADI_ETHER_BUFFER *buf;
+	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
+	int total_size = nobytes_buffer + RECV_BUFSIZE;
+
+	buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
+	frmbuf =
+	    (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
+					nobytes_buffer);
+
+	memset(buf, 0x00, nobytes_buffer);
+	buf->FrmData = frmbuf;
+	memset(frmbuf, 0xfe, RECV_BUFSIZE);
+
+	/* set up first desc to point to receive frame buffer */
+	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
+	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
+	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
+	buf->Dma[0].CONFIG.b_WNR = 1;	/* Write to memory */
+	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
+	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */
+
+	/* set up second desc to point to status word */
+	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
+	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
+	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
+	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
+	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
+	buf->Dma[1].CONFIG.b_NDSIZE = 5;	/* must be 0 when FLOW is 0 */
+	buf->Dma[1].CONFIG.b_FLOW = 7;	/* stop */
+
+	return buf;
+}
+
+ADI_ETHER_BUFFER *SetupTxBuffer(int no)
+{
+	ADI_ETHER_FRAME_BUFFER *frmbuf;
+	ADI_ETHER_BUFFER *buf;
+	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
+	int total_size = nobytes_buffer + RECV_BUFSIZE;
+
+	buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
+	frmbuf =
+	    (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
+					nobytes_buffer);
+
+	memset(buf, 0x00, nobytes_buffer);
+	buf->FrmData = frmbuf;
+	memset(frmbuf, 0x00, RECV_BUFSIZE);
+
+	/* set up first desc to point to receive frame buffer */
+	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
+	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
+	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
+	buf->Dma[0].CONFIG.b_WNR = 0;	/* Read to memory */
+	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
+	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */
+
+	/* set up second desc to point to status word */
+	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
+	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
+	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
+	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
+	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
+	buf->Dma[1].CONFIG.b_NDSIZE = 0;	/* must be 0 when FLOW is 0 */
+	buf->Dma[1].CONFIG.b_FLOW = 0;	/* stop */
+
+	return buf;
+}
+
+#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
+int ether_post_test(int flags)
+{
+	uchar buf[64];
+	int i, value = 0;
+	int length;
+
+	printf("\n--------");
+	bfin_EMAC_init(NULL, NULL);
+	/* construct the package */
+	buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
+	buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
+	buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
+	buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
+	buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
+	buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
+	buf[12] = 0x08;		/* Type: ARP */
+	buf[13] = 0x06;
+	buf[14] = 0x00;		/* Hardware type: Ethernet */
+	buf[15] = 0x01;
+	buf[16] = 0x08;		/* Protocal type: IP */
+	buf[17] = 0x00;
+	buf[18] = 0x06;		/* Hardware size    */
+	buf[19] = 0x04;		/* Protocol size    */
+	buf[20] = 0x00;		/* Opcode: request  */
+	buf[21] = 0x01;
+
+	for (i = 0; i < 42; i++)
+		buf[i + 22] = i;
+	printf("--------Send 64 bytes......\n");
+	bfin_EMAC_send(NULL, (volatile void *)buf, 64);
+	for (i = 0; i < 100; i++) {
+		udelay(10000);
+		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
+			value = 1;
+			break;
+		}
+	}
+	if (value == 0) {
+		printf("--------EMAC can't receive any data\n");
+		eth_halt();
+		return -1;
+	}
+	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
+	for (i = 0; i < length; i++) {
+		if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
+			printf("--------EMAC receive error data!\n");
+			eth_halt();
+			return -1;
+		}
+	}
+	printf("--------receive %d bytes, matched\n", length);
+	bfin_EMAC_halt(NULL);
+	return 0;
+}
+#endif
diff --git a/drivers/net/bfin_mac.h b/drivers/net/bfin_mac.h
new file mode 100644
index 0000000..c8a94d0
--- /dev/null
+++ b/drivers/net/bfin_mac.h
@@ -0,0 +1,89 @@
+/*
+ * bfin_mac.h - some defines/structures for the Blackfin on-chip MAC.
+ *
+ * Copyright (c) 2005-2008 Analog Device, Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MAC_H__
+#define __BFIN_MAC_H__
+
+#define PHYADDR			0x01
+#define NO_PHY_REGS		0x20
+
+#define DEFAULT_PHY_PHYID1	0x0007
+#define DEFAULT_PHY_PHYID2	0xC0A3
+#define PHY_MODECTL		0x00
+#define PHY_MODESTAT		0x01
+#define PHY_PHYID1		0x02
+#define PHY_PHYID2		0x03
+#define PHY_ANAR		0x04
+#define PHY_ANLPAR		0x05
+#define PHY_ANER		0x06
+
+#define PHY_RESET		0x8000
+#define PHY_ANEG_EN		0x1000
+#define PHY_DUPLEX		0x0100
+#define PHY_SPD_SET		0x2000
+
+#define RECV_BUFSIZE		(0x614)
+
+typedef volatile u32 reg32;
+typedef volatile u16 reg16;
+
+typedef struct ADI_DMA_CONFIG_REG {
+	u16 b_DMA_EN:1;		/* 0	Enabled				*/
+	u16 b_WNR:1;		/* 1	Direction			*/
+	u16 b_WDSIZE:2;		/* 2:3	Transfer word size		*/
+	u16 b_DMA2D:1;		/* 4	DMA mode			*/
+	u16 b_RESTART:1;	/* 5	Retain FIFO			*/
+	u16 b_DI_SEL:1;		/* 6	Data interrupt timing select	*/
+	u16 b_DI_EN:1;		/* 7	Data interrupt enabled		*/
+	u16 b_NDSIZE:4;		/* 8:11	Flex descriptor size		*/
+	u16 b_FLOW:3;		/* 12:14Flow				*/
+} ADI_DMA_CONFIG_REG;
+
+typedef struct adi_ether_frame_buffer {
+	u16 NoBytes;		/* the no. of following bytes	*/
+	u8 Dest[6];		/* destination MAC address	*/
+	u8 Srce[6];		/* source MAC address		*/
+	u16 LTfield;		/* length/type field		*/
+	u8 Data[0];		/* payload bytes		*/
+} ADI_ETHER_FRAME_BUFFER;
+/* 16 bytes/struct	*/
+
+typedef struct dma_descriptor {
+	struct dma_descriptor *NEXT_DESC_PTR;
+	u32 START_ADDR;
+	ADI_DMA_CONFIG_REG CONFIG;
+} DMA_DESCRIPTOR;
+/* 10 bytes/struct in 12 bytes */
+
+typedef struct adi_ether_buffer {
+	DMA_DESCRIPTOR Dma[2];		/* first for the frame, second for the status */
+	ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
+	struct adi_ether_buffer *pNext;	/* next buffer */
+	struct adi_ether_buffer *pPrev;	/* prev buffer */
+	u16 IPHdrChksum;		/* the IP header checksum */
+	u16 IPPayloadChksum;		/* the IP header and payload checksum */
+	volatile u32 StatusWord;	/* the frame status word */
+} ADI_ETHER_BUFFER;
+/* 40 bytes/struct in 44 bytes */
+
+static ADI_ETHER_BUFFER *SetupRxBuffer(int no);
+static ADI_ETHER_BUFFER *SetupTxBuffer(int no);
+
+static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd);
+static void bfin_EMAC_halt(struct eth_device *dev);
+static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length);
+static int bfin_EMAC_recv(struct eth_device *dev);
+
+static void PollMdcDone(void);
+static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
+static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
+static int SetupSystemRegs(int *opmode);
+
+static void bfin_EMAC_setup_addr(bd_t *bd);
+
+#endif
diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c
index b100657..99baeea 100644
--- a/drivers/net/ne2000.c
+++ b/drivers/net/ne2000.c
@@ -5,7 +5,6 @@ Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
 eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
 are GPL, so this is, of course, GPL.
 
-
 ==========================================================================
 
 dev/if_dp83902a.c
@@ -70,9 +69,7 @@ Add SNMP
 
 ####DESCRIPTIONEND####
 
-
 ==========================================================================
-
 */
 
 #include <common.h>
@@ -80,27 +77,11 @@ Add SNMP
 #include <net.h>
 #include <malloc.h>
 
-#ifdef CONFIG_DRIVER_NE2000
-
-/* wor around udelay resetting OCR */
-static void my_udelay(long us) {
-	long tmo;
-
-	tmo = get_timer (0) + us * CFG_HZ / 1000000; /* will this be much greater than 0 ? */
-	while (get_timer (0) < tmo);
-}
-
-#define mdelay(n)       my_udelay((n)*1000)
-
+#define mdelay(n)       udelay((n)*1000)
 /* forward definition of function used for the uboot interface */
 void uboot_push_packet_len(int len);
 void uboot_push_tx_done(int key, int val);
 
-/* timeout for tx/rx in s */
-#define TOUT 5
-
-#define ETHER_ADDR_LEN 6
-
 /*
   ------------------------------------------------------------------------
   Debugging details
@@ -118,17 +99,22 @@ void uboot_push_tx_done(int key, int val);
 #if DEBUG & 1
 #define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
 #define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
+#define PRINTK(args...) printf(args)
 #else
 #define DEBUG_FUNCTION() do {} while(0)
 #define DEBUG_LINE() do {} while(0)
+#define PRINTK(args...)
 #endif
 
-#include "ne2000.h"
+/* NE2000 base header file */
+#include "ne2000_base.h"
 
-#if DEBUG & 1
-#define PRINTK(args...) printf(args)
+#if defined(CONFIG_DRIVER_AX88796L)
+/* AX88796L support */
+#include "ax88796.h"
 #else
-#define PRINTK(args...)
+/* Basic NE2000 chip support */
+#include "ne2000.h"
 #endif
 
 static dp83902a_priv_data_t nic; /* just one instance of the card supported */
@@ -137,8 +123,7 @@ static bool
 dp83902a_init(void)
 {
 	dp83902a_priv_data_t *dp = &nic;
-	cyg_uint8* base;
-	int i;
+	u8* base;
 
 	DEBUG_FUNCTION();
 
@@ -147,6 +132,8 @@ dp83902a_init(void)
 
 	DEBUG_LINE();
 
+#if defined(NE2000_BASIC_INIT)
+	/* AX88796L doesn't need */
 	/* Prepare ESA */
 	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);  /* Select page 1 */
 	/* Use the address from the serial EEPROM */
@@ -163,6 +150,7 @@ dp83902a_init(void)
 	       dp->esa[4],
 	       dp->esa[5] );
 
+#endif	/* NE2000_BASIC_INIT */
 	return true;
 }
 
@@ -170,7 +158,7 @@ static void
 dp83902a_stop(void)
 {
 	dp83902a_priv_data_t *dp = &nic;
-	cyg_uint8 *base = dp->base;
+	u8 *base = dp->base;
 
 	DEBUG_FUNCTION();
 
@@ -188,10 +176,10 @@ dp83902a_stop(void)
   the hardware ready to send/receive packets.
 */
 static void
-dp83902a_start(unsigned char * enaddr)
+dp83902a_start(u8 * enaddr)
 {
 	dp83902a_priv_data_t *dp = &nic;
-	cyg_uint8 *base = dp->base;
+	u8 *base = dp->base;
 	int i;
 
 	DEBUG_FUNCTION();
@@ -206,15 +194,21 @@ dp83902a_start(unsigned char * enaddr)
 	dp->tx1 = dp->tx2 = 0;
 	dp->tx_next = dp->tx_buf1;
 	dp->tx_started = false;
+	dp->running = true;
 	DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
 	DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */
 	DP_OUT(base, DP_PSTOP, dp->rx_buf_end);	/* Receive ring end page */
 	dp->rx_next = dp->rx_buf_start-1;
+	dp->running = true;
 	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
 	DP_OUT(base, DP_IMR, DP_IMR_All);	/* Enable all interrupts */
 	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP);  /* Select page 1 */
 	DP_OUT(base, DP_P1_CURP, dp->rx_buf_start);   /* Current page - next free page for Rx */
+	dp->running = true;
 	for (i = 0;  i < ETHER_ADDR_LEN;  i++) {
+		/* FIXME */
+		/*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) +
+		 * 0x1400)) = enaddr[i];*/
 		DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
 	}
 	/* Enable and start device */
@@ -234,7 +228,7 @@ static void
 dp83902a_start_xmit(int start_page, int len)
 {
 	dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
-	cyg_uint8 *base = dp->base;
+	u8 *base = dp->base;
 
 	DEBUG_FUNCTION();
 
@@ -259,10 +253,10 @@ dp83902a_start_xmit(int start_page, int len)
   that there is free buffer space (dp->tx_next).
 */
 static void
-dp83902a_send(unsigned char *data, int total_len, unsigned long key)
+dp83902a_send(u8 *data, int total_len, u32 key)
 {
 	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
+	u8 *base = dp->base;
 	int len, start_page, pkt_len, i, isr;
 #if DEBUG & 4
 	int dx;
@@ -296,7 +290,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key)
 		/* but the code is extended a bit to do what Hitachi's monitor */
 		/* does (i.e., also read data). */
 
-		cyg_uint16 tmp;
+		u16 tmp;
 		int len = 1;
 
 		DP_OUT(base, DP_RSAL, 0x100-len);
@@ -322,7 +316,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key)
 
 	/* Put data into buffer */
 #if DEBUG & 4
-	printf(" sg buf %08lx len %08x\n ", (unsigned long) data, len);
+	printf(" sg buf %08lx len %08x\n ", (u32)data, len);
 	dx = 0;
 #endif
 	while (len > 0) {
@@ -330,6 +324,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key)
 		printf(" %02x", *data);
 		if (0 == (++dx % 16)) printf("\n ");
 #endif
+
 		DP_OUT_DATA(dp->data, *data++);
 		len--;
 	}
@@ -358,6 +353,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key)
 	do {
 		DP_IN(base, DP_ISR, isr);
 	} while ((isr & DP_ISR_RDC) == 0);
+
 	/* Then disable DMA */
 	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
 
@@ -383,9 +379,9 @@ static void
 dp83902a_RxEvent(void)
 {
 	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	unsigned char rsr;
-	unsigned char rcv_hdr[4];
+	u8 *base = dp->base;
+	u8 rsr;
+	u8 rcv_hdr[4];
 	int i, len, pkt, cur;
 
 	DEBUG_FUNCTION();
@@ -423,6 +419,7 @@ dp83902a_RxEvent(void)
 		CYGACC_CALL_IF_DELAY_US(10);
 #endif
 
+		/* read header (get data size)*/
 		for (i = 0;  i < sizeof(rcv_hdr);) {
 			DP_IN_DATA(dp->data, rcv_hdr[i++]);
 		}
@@ -432,7 +429,10 @@ dp83902a_RxEvent(void)
 		       rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
 #endif
 		len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
+
+		/* data read */
 		uboot_push_packet_len(len);
+
 		if (rcv_hdr[1] == dp->rx_buf_start)
 			DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1);
 		else
@@ -448,12 +448,12 @@ dp83902a_RxEvent(void)
   efficient processing in the upper layers of the stack.
 */
 static void
-dp83902a_recv(unsigned char *data, int len)
+dp83902a_recv(u8 *data, int len)
 {
 	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
+	u8 *base = dp->base;
 	int i, mlen;
-	cyg_uint8 saved_char = 0;
+	u8 saved_char = 0;
 	bool saved;
 #if DEBUG & 4
 	int dx;
@@ -482,7 +482,7 @@ dp83902a_recv(unsigned char *data, int len)
 		if (data) {
 			mlen = len;
 #if DEBUG & 4
-			printf(" sg buf %08lx len %08x \n", (unsigned long) data, mlen);
+			printf(" sg buf %08lx len %08x \n", (u32) data, mlen);
 			dx = 0;
 #endif
 			while (0 < mlen) {
@@ -495,7 +495,7 @@ dp83902a_recv(unsigned char *data, int len)
 				}
 
 				{
-					cyg_uint8 tmp;
+					u8 tmp;
 					DP_IN_DATA(dp->data, tmp);
 #if DEBUG & 4
 					printf(" %02x", tmp);
@@ -516,9 +516,9 @@ static void
 dp83902a_TxEvent(void)
 {
 	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	unsigned char tsr;
-	unsigned long key;
+	u8 *base = dp->base;
+	u8 tsr;
+	u32 key;
 
 	DEBUG_FUNCTION();
 
@@ -551,8 +551,8 @@ static void
 dp83902a_ClearCounters(void)
 {
 	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	cyg_uint8 cnt1, cnt2, cnt3;
+	u8 *base = dp->base;
+	u8 cnt1, cnt2, cnt3;
 
 	DP_IN(base, DP_FER, cnt1);
 	DP_IN(base, DP_CER, cnt2);
@@ -566,8 +566,8 @@ static void
 dp83902a_Overflow(void)
 {
 	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
-	cyg_uint8 *base = dp->base;
-	cyg_uint8 isr;
+	u8 *base = dp->base;
+	u8 isr;
 
 	/* Issue a stop command and wait 1.6ms for it to complete. */
 	DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
@@ -603,8 +603,8 @@ static void
 dp83902a_poll(void)
 {
 	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	unsigned char isr;
+	u8 *base = dp->base;
+	u8 isr;
 
 	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
 	DP_IN(base, DP_ISR, isr);
@@ -642,13 +642,13 @@ dp83902a_poll(void)
 /* find prom (taken from pc_net_cs.c from Linux) */
 
 #include "8390.h"
-
+/*
 typedef struct hw_info_t {
 	u_int	offset;
 	u_char	a0, a1, a2;
 	u_int	flags;
 } hw_info_t;
-
+*/
 #define DELAY_OUTPUT	0x01
 #define HAS_MISC_REG	0x02
 #define USE_BIG_BUF	0x04
@@ -731,102 +731,17 @@ static hw_info_t hw_info[] = {
 
 static hw_info_t default_info = { 0, 0, 0, 0, 0 };
 
-unsigned char dev_addr[6];
+u8 dev_addr[6];
 
 #define PCNET_CMD	0x00
 #define PCNET_DATAPORT	0x10	/* NatSemi-defined port window offset. */
 #define PCNET_RESET	0x1f	/* Issue a read to reset, a write to clear. */
 #define PCNET_MISC	0x18	/* For IBM CCAE and Socket EA cards */
 
-unsigned long nic_base;
-
-static void pcnet_reset_8390(void)
-{
-	int i, r;
-
-	PRINTK("nic base is %lx\n", nic_base);
-
-	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-	n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-
-	n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
-
-	for (i = 0; i < 100; i++) {
-		if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
-			break;
-		PRINTK("got %x in reset\n", r);
-		my_udelay(100);
-	}
-	n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
-
-	if (i == 100)
-		printf("pcnet_reset_8390() did not complete.\n");
-} /* pcnet_reset_8390 */
-
-static hw_info_t * get_prom(void ) {
-	unsigned char prom[32];
-	int i, j;
-	struct {
-		u_char value, offset;
-	} program_seq[] = {
-		{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
-		{0x48,	EN0_DCFG},	/* Set byte-wide (0x48) access. */
-		{0x00,	EN0_RCNTLO},	/* Clear the count regs. */
-		{0x00,	EN0_RCNTHI},
-		{0x00,	EN0_IMR},	/* Mask completion irq. */
-		{0xFF,	EN0_ISR},
-		{E8390_RXOFF, EN0_RXCR},	/* 0x20  Set to monitor */
-		{E8390_TXOFF, EN0_TXCR},	/* 0x02  and loopback mode. */
-		{32,	EN0_RCNTLO},
-		{0x00,	EN0_RCNTHI},
-		{0x00,	EN0_RSARLO},	/* DMA starting at 0x0000. */
-		{0x00,	EN0_RSARHI},
-		{E8390_RREAD+E8390_START, E8390_CMD},
-	};
-
-	PRINTK("trying to get MAC via prom reading\n");
-
-	pcnet_reset_8390();
-
-	mdelay(10);
-
-	for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++)
-		n2k_outb(program_seq[i].value, program_seq[i].offset);
-
-	PRINTK("PROM:");
-	for (i = 0; i < 32; i++) {
-		prom[i] = n2k_inb(PCNET_DATAPORT);
-		PRINTK(" %02x", prom[i]);
-	}
-	PRINTK("\n");
-	for (i = 0; i < NR_INFO; i++) {
-		if ((prom[0] == hw_info[i].a0) &&
-		    (prom[2] == hw_info[i].a1) &&
-		    (prom[4] == hw_info[i].a2)) {
-			PRINTK("matched board %d\n", i);
-			break;
-		}
-	}
-	if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
-		for (j = 0; j < 6; j++)
-			dev_addr[j] = prom[j<<1];
-		PRINTK("on exit i is %d/%ld\n", i, NR_INFO);
-		PRINTK("MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n",
-		       dev_addr[0],dev_addr[1],dev_addr[2],dev_addr[3],dev_addr[4],dev_addr[5]);
-		return (i < NR_INFO) ? hw_info+i : &default_info;
-	}
-	return NULL;
-}
+u32 nic_base;
 
 /* U-boot specific routines */
-
-
-static unsigned char *pbuf = NULL;
+static u8 *pbuf = NULL;
 
 static int pkey = -1;
 static int initialized=0;
@@ -839,7 +754,7 @@ void uboot_push_packet_len(int len) {
 	}
 	dp83902a_recv(&pbuf[0], len);
 
-	/* Just pass it to the upper layer */
+	/*Just pass it to the upper layer*/
 	NetReceive(&pbuf[0], len);
 }
 
@@ -864,7 +779,7 @@ int eth_init(bd_t *bd) {
 
 #ifdef CONFIG_DRIVER_NE2000_CCR
 	{
-		volatile unsigned char *p =  (volatile unsigned char *) CONFIG_DRIVER_NE2000_CCR;
+		vu_char *p =  (vu_char *) CONFIG_DRIVER_NE2000_CCR;
 
 		PRINTK("CCR before is %x\n", *p);
 		*p = CONFIG_DRIVER_NE2000_VAL;
@@ -873,9 +788,9 @@ int eth_init(bd_t *bd) {
 #endif
 
 	nic_base = CONFIG_DRIVER_NE2000_BASE;
-	nic.base = (cyg_uint8 *) CONFIG_DRIVER_NE2000_BASE;
+	nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
 
-	r = get_prom();
+	r = get_prom(dev_addr);
 	if (!r)
 		return -1;
 
@@ -886,22 +801,23 @@ int eth_init(bd_t *bd) {
 	PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr);
 	setenv ("ethaddr", ethaddr);
 
-
-#define DP_DATA		0x10
 	nic.data = nic.base + DP_DATA;
-	nic.tx_buf1 = 0x40;
-	nic.tx_buf2 = 0x48;
-	nic.rx_buf_start = 0x50;
-	nic.rx_buf_end = 0x80;
+	nic.tx_buf1 = START_PG;
+	nic.tx_buf2 = START_PG2;
+	nic.rx_buf_start = RX_START;
+	nic.rx_buf_end = RX_END;
 
 	if (dp83902a_init() == false)
 		return -1;
+
 	dp83902a_start(dev_addr);
 	initialized=1;
+
 	return 0;
 }
 
 void eth_halt() {
+
 	PRINTK("### eth_halt\n");
 	if(initialized)
 		dp83902a_stop();
@@ -920,7 +836,7 @@ int eth_send(volatile void *packet, int length) {
 
 	pkey = -1;
 
-	dp83902a_send((unsigned char *) packet, length, 666);
+	dp83902a_send((u8 *) packet, length, 666);
 	tmo = get_timer (0) + TOUT * CFG_HZ;
 	while(1) {
 		dp83902a_poll();
@@ -936,4 +852,3 @@ int eth_send(volatile void *packet, int length) {
 	}
 	return 0;
 }
-#endif
diff --git a/drivers/net/ne2000.h b/drivers/net/ne2000.h
index c13d9f0..d324a00 100644
--- a/drivers/net/ne2000.h
+++ b/drivers/net/ne2000.h
@@ -5,7 +5,6 @@ Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
 eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
 are GPL, so this is, of course, GPL.
 
-
 ==========================================================================
 
       dev/dp83902a.h
@@ -67,213 +66,114 @@ are GPL, so this is, of course, GPL.
 ####DESCRIPTIONEND####
 
 ==========================================================================
-
 */
 
 /*
- ------------------------------------------------------------------------
- Macros for accessing DP registers
- These can be overridden by the platform header
-*/
-
-#define DP_IN(_b_, _o_, _d_)  (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_)))
-#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_)
-
-#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (volatile unsigned char *) ((_b_)))
-#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_)
-
-
-/* here is all the data */
-
-#define cyg_uint8 unsigned char
-#define cyg_uint16 unsigned short
-#define bool int
-
-#define false 0
-#define true 1
-
-#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
-#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X)
-
-typedef struct dp83902a_priv_data {
-    cyg_uint8* base;
-    cyg_uint8* data;
-    cyg_uint8* reset;
-    int tx_next;           /* First free Tx page */
-    int tx_int;            /* Expecting interrupt from this buffer */
-    int rx_next;           /* First free Rx page */
-    int tx1, tx2;          /* Page numbers for Tx buffers */
-    unsigned long tx1_key, tx2_key;   /* Used to ack when packet sent */
-    int tx1_len, tx2_len;
-    bool tx_started, running, hardwired_esa;
-    cyg_uint8 esa[6];
-    void* plf_priv;
-
-    /* Buffer allocation */
-    int tx_buf1, tx_buf2;
-    int rx_buf_start, rx_buf_end;
-} dp83902a_priv_data_t;
-
-/*
- ------------------------------------------------------------------------
- Some forward declarations
-*/
-static void dp83902a_poll(void);
-
-/* ------------------------------------------------------------------------ */
-/* Register offsets */
-
-#define DP_CR          0x00
-#define DP_CLDA0       0x01
-#define DP_PSTART      0x01             /* write */
-#define DP_CLDA1       0x02
-#define DP_PSTOP       0x02             /* write */
-#define DP_BNDRY       0x03
-#define DP_TSR         0x04
-#define DP_TPSR        0x04             /* write */
-#define DP_NCR         0x05
-#define DP_TBCL        0x05             /* write */
-#define DP_FIFO        0x06
-#define DP_TBCH        0x06             /* write */
-#define DP_ISR         0x07
-#define DP_CRDA0       0x08
-#define DP_RSAL        0x08             /* write */
-#define DP_CRDA1       0x09
-#define DP_RSAH        0x09             /* write */
-#define DP_RBCL        0x0a             /* write */
-#define DP_RBCH        0x0b             /* write */
-#define DP_RSR         0x0c
-#define DP_RCR         0x0c             /* write */
-#define DP_FER         0x0d
-#define DP_TCR         0x0d             /* write */
-#define DP_CER         0x0e
-#define DP_DCR         0x0e             /* write */
-#define DP_MISSED      0x0f
-#define DP_IMR         0x0f             /* write */
-#define DP_DATAPORT    0x10             /* "eprom" data port */
-
-#define DP_P1_CR       0x00
-#define DP_P1_PAR0     0x01
-#define DP_P1_PAR1     0x02
-#define DP_P1_PAR2     0x03
-#define DP_P1_PAR3     0x04
-#define DP_P1_PAR4     0x05
-#define DP_P1_PAR5     0x06
-#define DP_P1_CURP     0x07
-#define DP_P1_MAR0     0x08
-#define DP_P1_MAR1     0x09
-#define DP_P1_MAR2     0x0a
-#define DP_P1_MAR3     0x0b
-#define DP_P1_MAR4     0x0c
-#define DP_P1_MAR5     0x0d
-#define DP_P1_MAR6     0x0e
-#define DP_P1_MAR7     0x0f
-
-#define DP_P2_CR       0x00
-#define DP_P2_PSTART   0x01
-#define DP_P2_CLDA0    0x01             /* write */
-#define DP_P2_PSTOP    0x02
-#define DP_P2_CLDA1    0x02             /* write */
-#define DP_P2_RNPP     0x03
-#define DP_P2_TPSR     0x04
-#define DP_P2_LNPP     0x05
-#define DP_P2_ACH      0x06
-#define DP_P2_ACL      0x07
-#define DP_P2_RCR      0x0c
-#define DP_P2_TCR      0x0d
-#define DP_P2_DCR      0x0e
-#define DP_P2_IMR      0x0f
-
-/* Command register - common to all pages */
-
-#define DP_CR_STOP    0x01   /* Stop: software reset */
-#define DP_CR_START   0x02   /* Start: initialize device */
-#define DP_CR_TXPKT   0x04   /* Transmit packet */
-#define DP_CR_RDMA    0x08   /* Read DMA  (recv data from device) */
-#define DP_CR_WDMA    0x10   /* Write DMA (send data to device) */
-#define DP_CR_SEND    0x18   /* Send packet */
-#define DP_CR_NODMA   0x20   /* Remote (or no) DMA */
-#define DP_CR_PAGE0   0x00   /* Page select */
-#define DP_CR_PAGE1   0x40
-#define DP_CR_PAGE2   0x80
-#define DP_CR_PAGEMSK 0x3F   /* Used to mask out page bits */
-
-/* Data configuration register */
-
-#define DP_DCR_WTS    0x01   /* 1=16 bit word transfers */
-#define DP_DCR_BOS    0x02   /* 1=Little Endian */
-#define DP_DCR_LAS    0x04   /* 1=Single 32 bit DMA mode */
-#define DP_DCR_LS     0x08   /* 1=normal mode, 0=loopback */
-#define DP_DCR_ARM    0x10   /* 0=no send command (program I/O) */
-#define DP_DCR_FIFO_1 0x00   /* FIFO threshold */
-#define DP_DCR_FIFO_2 0x20
-#define DP_DCR_FIFO_4 0x40
-#define DP_DCR_FIFO_6 0x60
-
-#define DP_DCR_INIT   (DP_DCR_LS|DP_DCR_FIFO_4)
-
-/* Interrupt status register */
-
-#define DP_ISR_RxP    0x01   /* Packet received */
-#define DP_ISR_TxP    0x02   /* Packet transmitted */
-#define DP_ISR_RxE    0x04   /* Receive error */
-#define DP_ISR_TxE    0x08   /* Transmit error */
-#define DP_ISR_OFLW   0x10   /* Receive overflow */
-#define DP_ISR_CNT    0x20   /* Tally counters need emptying */
-#define DP_ISR_RDC    0x40   /* Remote DMA complete */
-#define DP_ISR_RESET  0x80   /* Device has reset (shutdown, error) */
-
-/* Interrupt mask register */
-
-#define DP_IMR_RxP    0x01   /* Packet received */
-#define DP_IMR_TxP    0x02   /* Packet transmitted */
-#define DP_IMR_RxE    0x04   /* Receive error */
-#define DP_IMR_TxE    0x08   /* Transmit error */
-#define DP_IMR_OFLW   0x10   /* Receive overflow */
-#define DP_IMR_CNT    0x20   /* Tall counters need emptying */
-#define DP_IMR_RDC    0x40   /* Remote DMA complete */
-
-#define DP_IMR_All    0x3F   /* Everything but remote DMA */
-
-/* Receiver control register */
-
-#define DP_RCR_SEP    0x01   /* Save bad(error) packets */
-#define DP_RCR_AR     0x02   /* Accept runt packets */
-#define DP_RCR_AB     0x04   /* Accept broadcast packets */
-#define DP_RCR_AM     0x08   /* Accept multicast packets */
-#define DP_RCR_PROM   0x10   /* Promiscuous mode */
-#define DP_RCR_MON    0x20   /* Monitor mode - 1=accept no packets */
-
-/* Receiver status register */
-
-#define DP_RSR_RxP    0x01   /* Packet received */
-#define DP_RSR_CRC    0x02   /* CRC error */
-#define DP_RSR_FRAME  0x04   /* Framing error */
-#define DP_RSR_FO     0x08   /* FIFO overrun */
-#define DP_RSR_MISS   0x10   /* Missed packet */
-#define DP_RSR_PHY    0x20   /* 0=pad match, 1=mad match */
-#define DP_RSR_DIS    0x40   /* Receiver disabled */
-#define DP_RSR_DFR    0x80   /* Receiver processing deferred */
-
-/* Transmitter control register */
-
-#define DP_TCR_NOCRC  0x01   /* 1=inhibit CRC */
-#define DP_TCR_NORMAL 0x00   /* Normal transmitter operation */
-#define DP_TCR_LOCAL  0x02   /* Internal NIC loopback */
-#define DP_TCR_INLOOP 0x04   /* Full internal loopback */
-#define DP_TCR_OUTLOOP 0x08  /* External loopback */
-#define DP_TCR_ATD    0x10   /* Auto transmit disable */
-#define DP_TCR_OFFSET 0x20   /* Collision offset adjust */
-
-/* Transmit status register */
-
-#define DP_TSR_TxP    0x01   /* Packet transmitted */
-#define DP_TSR_COL    0x04   /* Collision (at least one) */
-#define DP_TSR_ABT    0x08   /* Aborted because of too many collisions */
-#define DP_TSR_CRS    0x10   /* Lost carrier */
-#define DP_TSR_FU     0x20   /* FIFO underrun */
-#define DP_TSR_CDH    0x40   /* Collision Detect Heartbeat */
-#define DP_TSR_OWC    0x80   /* Collision outside normal window */
-
-#define IEEE_8023_MAX_FRAME         1518    /* Largest possible ethernet frame */
-#define IEEE_8023_MIN_FRAME           64    /* Smallest possible ethernet frame */
+ * NE2000 support header file.
+ *		Created by Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#ifndef __DRIVERS_NE2000_H__
+#define __DRIVERS_NE2000_H__
+
+/* Enable NE2000 basic init function */
+#define NE2000_BASIC_INIT
+
+#define DP_DATA     0x10
+#define START_PG    0x50    /* First page of TX buffer */
+#define STOP_PG     0x80    /* Last page +1 of RX ring */
+
+#define RX_START    0x50
+#define RX_END      0x80
+
+#define DP_IN(_b_, _o_, _d_)  (_d_) = *( (vu_char *) ((_b_)+(_o_)))
+#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_)
+#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (vu_char *) ((_b_)))
+#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_)
+
+static void pcnet_reset_8390(void)
+{
+	int i, r;
+
+	PRINTK("nic base is %lx\n", nic_base);
+
+	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
+	n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
+	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
+	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
+	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+
+	n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
+
+	for (i = 0; i < 100; i++) {
+		if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
+			break;
+		PRINTK("got %x in reset\n", r);
+		udelay(100);
+	}
+	n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
+
+	if (i == 100)
+		printf("pcnet_reset_8390() did not complete.\n");
+} /* pcnet_reset_8390 */
+
+int get_prom(u8* mac_addr)
+{
+	u8 prom[32];
+	int i, j;
+	struct {
+		u_char value, offset;
+	} program_seq[] = {
+		{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
+		{0x48,  EN0_DCFG},		/* Set byte-wide (0x48) access. */
+		{0x00,  EN0_RCNTLO},		/* Clear the count regs. */
+		{0x00,  EN0_RCNTHI},
+		{0x00,  EN0_IMR},		/* Mask completion irq. */
+		{0xFF,  EN0_ISR},
+		{E8390_RXOFF, EN0_RXCR},	/* 0x20  Set to monitor */
+		{E8390_TXOFF, EN0_TXCR},	/* 0x02  and loopback mode. */
+		{32,    EN0_RCNTLO},
+		{0x00,  EN0_RCNTHI},
+		{0x00,  EN0_RSARLO},		/* DMA starting at 0x0000. */
+		{0x00,  EN0_RSARHI},
+		{E8390_RREAD+E8390_START, E8390_CMD},
+	};
+
+	PRINTK ("trying to get MAC via prom reading\n");
+
+	pcnet_reset_8390 ();
+
+	mdelay (10);
+
+	for (i = 0; i < sizeof (program_seq) / sizeof (program_seq[0]); i++)
+		n2k_outb (program_seq[i].value, program_seq[i].offset);
+
+	PRINTK ("PROM:");
+	for (i = 0; i < 32; i++) {
+		prom[i] = n2k_inb (PCNET_DATAPORT);
+		PRINTK (" %02x", prom[i]);
+	}
+	PRINTK ("\n");
+	for (i = 0; i < NR_INFO; i++) {
+		if ((prom[0] == hw_info[i].a0) &&
+		    (prom[2] == hw_info[i].a1) &&
+		    (prom[4] == hw_info[i].a2)) {
+			PRINTK ("matched board %d\n", i);
+			break;
+		}
+	}
+	if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
+		PRINTK ("on exit i is %d/%ld\n", i, NR_INFO);
+		PRINTK ("MAC address is ");
+		for (j = 0; j < 6; j++) {
+			mac_addr[j] = prom[j << 1];
+			PRINTK ("%02x:", mac_addr[i]);
+		}
+		PRINTK ("\n");
+		return (i < NR_INFO) ? i : 0;
+	}
+	return NULL;
+}
+#endif /* __DRIVERS_NE2000_H__ */
diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h
new file mode 100644
index 0000000..1badf62
--- /dev/null
+++ b/drivers/net/ne2000_base.h
@@ -0,0 +1,282 @@
+/*
+Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>
+
+Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
+eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
+are GPL, so this is, of course, GPL.
+
+
+==========================================================================
+
+      dev/dp83902a.h
+
+      National Semiconductor DP83902a ethernet chip
+
+==========================================================================
+####ECOSGPLCOPYRIGHTBEGIN####
+ -------------------------------------------
+ This file is part of eCos, the Embedded Configurable Operating System.
+ Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+
+ eCos is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 2 or (at your option) any later version.
+
+ eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with eCos; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+ As a special exception, if other files instantiate templates or use macros
+ or inline functions from this file, or you compile this file and link it
+ with other works to produce a work based on this file, this file does not
+ by itself cause the resulting work to be covered by the GNU General Public
+ License. However the source code for this file must still be made available
+ in accordance with section (3) of the GNU General Public License.
+
+ This exception does not invalidate any other reasons why a work based on
+ this file might be covered by the GNU General Public License.
+
+ Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+ at http://sources.redhat.com/ecos/ecos-license/
+ -------------------------------------------
+####ECOSGPLCOPYRIGHTEND####
+####BSDCOPYRIGHTBEGIN####
+
+ -------------------------------------------
+
+ Portions of this software may have been derived from OpenBSD or other sources,
+ and are covered by the appropriate copyright disclaimers included herein.
+
+ -------------------------------------------
+
+####BSDCOPYRIGHTEND####
+==========================================================================
+#####DESCRIPTIONBEGIN####
+
+ Author(s):    gthomas
+ Contributors: gthomas, jskov
+ Date:         2001-06-13
+ Purpose:
+ Description:
+
+####DESCRIPTIONEND####
+
+==========================================================================
+
+*/
+
+/*
+ ------------------------------------------------------------------------
+ Macros for accessing DP registers
+ These can be overridden by the platform header
+*/
+
+#define bool int
+
+#define false 0
+#define true 1
+
+/* timeout for tx/rx in s */
+#define TOUT 5
+/* Ether MAC address size */
+#define ETHER_ADDR_LEN 6
+
+
+#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
+#define CYGACC_CALL_IF_DELAY_US(X) udelay(X)
+
+/* H/W infomation struct */
+typedef struct hw_info_t {
+    u32   offset;
+    u8  a0, a1, a2;
+    u32   flags;
+} hw_info_t;
+
+typedef struct dp83902a_priv_data {
+    u8* base;
+    u8* data;
+    u8* reset;
+    int tx_next;           /* First free Tx page */
+    int tx_int;            /* Expecting interrupt from this buffer */
+    int rx_next;           /* First free Rx page */
+    int tx1, tx2;          /* Page numbers for Tx buffers */
+    u32 tx1_key, tx2_key;   /* Used to ack when packet sent */
+    int tx1_len, tx2_len;
+    bool tx_started, running, hardwired_esa;
+    u8 esa[6];
+    void* plf_priv;
+
+    /* Buffer allocation */
+    int tx_buf1, tx_buf2;
+    int rx_buf_start, rx_buf_end;
+} dp83902a_priv_data_t;
+
+/*
+ ------------------------------------------------------------------------
+ Some forward declarations
+*/
+int get_prom( u8* mac_addr);
+static void dp83902a_poll(void);
+
+/* ------------------------------------------------------------------------ */
+/* Register offsets */
+
+#define DP_CR          0x00
+#define DP_CLDA0       0x01
+#define DP_PSTART      0x01             /* write */
+#define DP_CLDA1       0x02
+#define DP_PSTOP       0x02             /* write */
+#define DP_BNDRY       0x03
+#define DP_TSR         0x04
+#define DP_TPSR        0x04             /* write */
+#define DP_NCR         0x05
+#define DP_TBCL        0x05             /* write */
+#define DP_FIFO        0x06
+#define DP_TBCH        0x06             /* write */
+#define DP_ISR         0x07
+#define DP_CRDA0       0x08
+#define DP_RSAL        0x08             /* write */
+#define DP_CRDA1       0x09
+#define DP_RSAH        0x09             /* write */
+#define DP_RBCL        0x0a             /* write */
+#define DP_RBCH        0x0b             /* write */
+#define DP_RSR         0x0c
+#define DP_RCR         0x0c             /* write */
+#define DP_FER         0x0d
+#define DP_TCR         0x0d             /* write */
+#define DP_CER         0x0e
+#define DP_DCR         0x0e             /* write */
+#define DP_MISSED      0x0f
+#define DP_IMR         0x0f             /* write */
+#define DP_DATAPORT    0x10             /* "eprom" data port */
+
+#define DP_P1_CR       0x00
+#define DP_P1_PAR0     0x01
+#define DP_P1_PAR1     0x02
+#define DP_P1_PAR2     0x03
+#define DP_P1_PAR3     0x04
+#define DP_P1_PAR4     0x05
+#define DP_P1_PAR5     0x06
+#define DP_P1_CURP     0x07
+#define DP_P1_MAR0     0x08
+#define DP_P1_MAR1     0x09
+#define DP_P1_MAR2     0x0a
+#define DP_P1_MAR3     0x0b
+#define DP_P1_MAR4     0x0c
+#define DP_P1_MAR5     0x0d
+#define DP_P1_MAR6     0x0e
+#define DP_P1_MAR7     0x0f
+
+#define DP_P2_CR       0x00
+#define DP_P2_PSTART   0x01
+#define DP_P2_CLDA0    0x01             /* write */
+#define DP_P2_PSTOP    0x02
+#define DP_P2_CLDA1    0x02             /* write */
+#define DP_P2_RNPP     0x03
+#define DP_P2_TPSR     0x04
+#define DP_P2_LNPP     0x05
+#define DP_P2_ACH      0x06
+#define DP_P2_ACL      0x07
+#define DP_P2_RCR      0x0c
+#define DP_P2_TCR      0x0d
+#define DP_P2_DCR      0x0e
+#define DP_P2_IMR      0x0f
+
+/* Command register - common to all pages */
+
+#define DP_CR_STOP    0x01   /* Stop: software reset */
+#define DP_CR_START   0x02   /* Start: initialize device */
+#define DP_CR_TXPKT   0x04   /* Transmit packet */
+#define DP_CR_RDMA    0x08   /* Read DMA  (recv data from device) */
+#define DP_CR_WDMA    0x10   /* Write DMA (send data to device) */
+#define DP_CR_SEND    0x18   /* Send packet */
+#define DP_CR_NODMA   0x20   /* Remote (or no) DMA */
+#define DP_CR_PAGE0   0x00   /* Page select */
+#define DP_CR_PAGE1   0x40
+#define DP_CR_PAGE2   0x80
+#define DP_CR_PAGEMSK 0x3F   /* Used to mask out page bits */
+
+/* Data configuration register */
+
+#define DP_DCR_WTS    0x01   /* 1=16 bit word transfers */
+#define DP_DCR_BOS    0x02   /* 1=Little Endian */
+#define DP_DCR_LAS    0x04   /* 1=Single 32 bit DMA mode */
+#define DP_DCR_LS     0x08   /* 1=normal mode, 0=loopback */
+#define DP_DCR_ARM    0x10   /* 0=no send command (program I/O) */
+#define DP_DCR_FIFO_1 0x00   /* FIFO threshold */
+#define DP_DCR_FIFO_2 0x20
+#define DP_DCR_FIFO_4 0x40
+#define DP_DCR_FIFO_6 0x60
+
+#define DP_DCR_INIT   (DP_DCR_LS|DP_DCR_FIFO_4)
+
+/* Interrupt status register */
+
+#define DP_ISR_RxP    0x01   /* Packet received */
+#define DP_ISR_TxP    0x02   /* Packet transmitted */
+#define DP_ISR_RxE    0x04   /* Receive error */
+#define DP_ISR_TxE    0x08   /* Transmit error */
+#define DP_ISR_OFLW   0x10   /* Receive overflow */
+#define DP_ISR_CNT    0x20   /* Tally counters need emptying */
+#define DP_ISR_RDC    0x40   /* Remote DMA complete */
+#define DP_ISR_RESET  0x80   /* Device has reset (shutdown, error) */
+
+/* Interrupt mask register */
+
+#define DP_IMR_RxP    0x01   /* Packet received */
+#define DP_IMR_TxP    0x02   /* Packet transmitted */
+#define DP_IMR_RxE    0x04   /* Receive error */
+#define DP_IMR_TxE    0x08   /* Transmit error */
+#define DP_IMR_OFLW   0x10   /* Receive overflow */
+#define DP_IMR_CNT    0x20   /* Tall counters need emptying */
+#define DP_IMR_RDC    0x40   /* Remote DMA complete */
+
+#define DP_IMR_All    0x3F   /* Everything but remote DMA */
+
+/* Receiver control register */
+
+#define DP_RCR_SEP    0x01   /* Save bad(error) packets */
+#define DP_RCR_AR     0x02   /* Accept runt packets */
+#define DP_RCR_AB     0x04   /* Accept broadcast packets */
+#define DP_RCR_AM     0x08   /* Accept multicast packets */
+#define DP_RCR_PROM   0x10   /* Promiscuous mode */
+#define DP_RCR_MON    0x20   /* Monitor mode - 1=accept no packets */
+
+/* Receiver status register */
+
+#define DP_RSR_RxP    0x01   /* Packet received */
+#define DP_RSR_CRC    0x02   /* CRC error */
+#define DP_RSR_FRAME  0x04   /* Framing error */
+#define DP_RSR_FO     0x08   /* FIFO overrun */
+#define DP_RSR_MISS   0x10   /* Missed packet */
+#define DP_RSR_PHY    0x20   /* 0=pad match, 1=mad match */
+#define DP_RSR_DIS    0x40   /* Receiver disabled */
+#define DP_RSR_DFR    0x80   /* Receiver processing deferred */
+
+/* Transmitter control register */
+
+#define DP_TCR_NOCRC  0x01   /* 1=inhibit CRC */
+#define DP_TCR_NORMAL 0x00   /* Normal transmitter operation */
+#define DP_TCR_LOCAL  0x02   /* Internal NIC loopback */
+#define DP_TCR_INLOOP 0x04   /* Full internal loopback */
+#define DP_TCR_OUTLOOP 0x08  /* External loopback */
+#define DP_TCR_ATD    0x10   /* Auto transmit disable */
+#define DP_TCR_OFFSET 0x20   /* Collision offset adjust */
+
+/* Transmit status register */
+
+#define DP_TSR_TxP    0x01   /* Packet transmitted */
+#define DP_TSR_COL    0x04   /* Collision (at least one) */
+#define DP_TSR_ABT    0x08   /* Aborted because of too many collisions */
+#define DP_TSR_CRS    0x10   /* Lost carrier */
+#define DP_TSR_FU     0x20   /* FIFO underrun */
+#define DP_TSR_CDH    0x40   /* Collision Detect Heartbeat */
+#define DP_TSR_OWC    0x80   /* Collision outside normal window */
+
+#define IEEE_8023_MAX_FRAME         1518    /* Largest possible ethernet frame */
+#define IEEE_8023_MIN_FRAME           64    /* Smallest possible ethernet frame */
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index d03cbc3..8dcbb3e 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -186,7 +186,7 @@ typedef unsigned long int 		dword;
 #ifdef CONFIG_ADNPESC1
 #define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
 #elif CONFIG_BLACKFIN
-#define	SMC_inw(r) 	({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;})
+#define	SMC_inw(r) 	({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;})
 #else
 #define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
 #endif
@@ -195,7 +195,7 @@ typedef unsigned long int 		dword;
 #ifdef CONFIG_ADNPESC1
 #define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
 #elif CONFIG_BLACKFIN
-#define	SMC_outw(d,r)	{(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");}
+#define	SMC_outw(d,r)	{(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d); SSYNC();}
 #else
 #define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
 #endif
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e91d9ea..431a8d2 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -583,10 +583,11 @@ uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
 	uint speed;
 
 	mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
-	if ((mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) &&
-		!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
+	if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
 		int i = 0;
 
+		/* in case of timeout ->link is cleared */
+		priv->link = 1;
 		puts("Waiting for PHY realtime link");
 		while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
 			/* Timeout reached ? */
diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
new file mode 100644
index 0000000..4095bce
--- /dev/null
+++ b/drivers/net/vsc7385.c
@@ -0,0 +1,101 @@
+/*
+ * Vitesse 7385 Switch Firmware Upload
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.  This file is licensed
+ * under the terms of the GNU General Public License version 2.  This
+ * program is licensed "as is" without any warranty of any kind, whether
+ * express or implied.
+ *
+ * This module uploads proprietary firmware for the Vitesse VSC7385 5-port
+ * switch.
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_VSC7385_ENET
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+/*
+ * Upload a Vitesse VSC7385 firmware image to the hardware
+ *
+ * This function takes a pointer to a VSC7385 firmware image and a size, and
+ * uploads that firmware to the VSC7385.
+ *
+ * This firmware is typically located at a board-specific flash address,
+ * and the size is typically 8KB.
+ *
+ * The firmware is Vitesse proprietary.
+ *
+ * Further details on the register information can be obtained from Vitesse.
+ */
+int vsc7385_upload_firmware(void *firmware, unsigned int size)
+{
+	u8 *fw = firmware;
+	unsigned int i;
+
+	u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050);
+	u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040);
+	u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044);
+	u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048);
+	u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070);
+#ifdef DEBUG
+	u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060);
+#endif
+
+	out_be32(gloreset, 3);
+	udelay(200);
+
+	out_be32(icpu_ctrl, 0x8E);
+	udelay(20);
+
+	out_be32(icpu_rom_map, 1);
+	udelay(20);
+
+	/* Write the firmware to I-RAM */
+	out_be32(icpu_addr, 0);
+	udelay(20);
+
+	for (i = 0; i < size; i++) {
+		out_be32(icpu_data, fw[i]);
+		udelay(20);
+		if (ctrlc())
+			return -EINTR;
+	}
+
+	/* Read back and compare */
+	out_be32(icpu_addr, 0);
+	udelay(20);
+
+	for (i = 0; i < size; i++) {
+		u8 value;
+
+		value = (u8) in_be32(icpu_data);
+		udelay(20);
+		if (value != fw[i]) {
+			debug("VSC7385: Upload mismatch: address 0x%x, "
+			      "read value 0x%x, image value 0x%x\n",
+			      i, value, fw[i]);
+
+			return -EIO;
+		}
+		if (ctrlc())
+			break;
+	}
+
+	out_be32(icpu_ctrl, 0x0B);
+	udelay(20);
+
+#ifdef DEBUG
+	printf("VSC7385: Chip ID is %08x\n", in_be32(chipid));
+	udelay(20);
+#endif
+
+	return 0;
+}
+
+#endif