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| author | Andre Schwarz <andre.schwarz@matrix-vision.de> | 2008-04-29 19:18:32 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-05-03 23:27:04 +0200 |
| commit | 9acde129cc3f9c1b3bc11a821480dd446774d618 (patch) | |
| tree | 408342b2cea52b5b979c0ca86bb5c4af95027076 /drivers/net/tsec.h | |
| parent | 27c38689d0cfde0e444239345f97b5eecc9f4067 (diff) | |
| download | u-boot-imx-9acde129cc3f9c1b3bc11a821480dd446774d618.zip u-boot-imx-9acde129cc3f9c1b3bc11a821480dd446774d618.tar.gz u-boot-imx-9acde129cc3f9c1b3bc11a821480dd446774d618.tar.bz2 | |
TSEC: add config options for VSC8601 RGMII PHY
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
--
drivers/net/tsec.c | 6 ++++++
drivers/net/tsec.h | 3 +++
2 files changed, 9 insertions(+), 0 deletions(-)
Diffstat (limited to 'drivers/net/tsec.h')
| -rw-r--r-- | drivers/net/tsec.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h index cfa7d1a..597ea1d 100644 --- a/drivers/net/tsec.h +++ b/drivers/net/tsec.h @@ -112,6 +112,8 @@ #define MIIM_GBIT_CONTROL 0x9 #define MIIM_GBIT_CONTROL_INIT 0xe00 +#define MIIM_EXT_PAGE_ACCESS 0x1f + /* Broadcom BCM54xx -- taken from linux sungem_phy */ #define MIIM_BCM54xx_AUXSTATUS 0x19 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 @@ -161,8 +163,9 @@ /* Entry for Vitesse VSC8601 regs starts here (Not complete) */ /* Vitesse VSC8601 Extended PHY Control Register 1 */ -#define MIIM_VSC8601_EPHY_CON 0x17 +#define MIIM_VSC8601_EPHY_CON 0x17 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 +#define MIIM_VSC8601_SKEW_CTRL 0x1c /* 88E1011 PHY Status Register */ #define MIIM_88E1011_PHY_STATUS 0x11 @@ -177,9 +180,9 @@ #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 /* 88E1111 PHY LED Control Register */ -#define MIIM_88E1111_PHY_LED_CONTROL 24 -#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 -#define MIIM_88E1111_PHY_LED_COMBINE 0x411C +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C /* 88E1145 Extended PHY Specific Control Register */ #define MIIM_88E1145_PHY_EXT_CR 20 |