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| author | Wolfgang Denk <wd@denx.de> | 2008-10-19 02:35:50 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-21 11:25:39 +0200 |
| commit | 8ed44d91c8122d00368523b0b746691c895d3b3c (patch) | |
| tree | 7e2ff620c5b378aa82208c3e7a99e2a56570ddb7 /drivers/net/tigon3.c | |
| parent | 08ef89ecd174969b3544f3f0c7cd1de3c57f737b (diff) | |
| download | u-boot-imx-8ed44d91c8122d00368523b0b746691c895d3b3c.zip u-boot-imx-8ed44d91c8122d00368523b0b746691c895d3b3c.tar.gz u-boot-imx-8ed44d91c8122d00368523b0b746691c895d3b3c.tar.bz2 | |
Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'drivers/net/tigon3.c')
| -rw-r--r-- | drivers/net/tigon3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/tigon3.c b/drivers/net/tigon3.c index ab448b0..e4e004e 100644 --- a/drivers/net/tigon3.c +++ b/drivers/net/tigon3.c @@ -2247,7 +2247,7 @@ LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice) REG_WR (pDevice, Grc.Mode, Value32); /* Setup the timer prescalar register. */ - REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */ + REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66MHz. */ /* Set up the MBUF pool base address and size. */ REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); |