Big white-space cleanup.

This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>

10 files changed, 313 insertions, 314 deletions

diff --git a/drivers/net/sk98lin/h/skdebug.h b/drivers/net/sk98lin/h/skdebug.h
index cf5b5ad..5feda92 100644
--- a/drivers/net/sk98lin/h/skdebug.h
+++ b/drivers/net/sk98lin/h/skdebug.h
@@ -73,8 +73,8 @@
 #ifdef	DEBUG
 #ifndef SK_DBG_MSG
 #define SK_DBG_MSG(pAC,comp,cat,arg) \
-		if ( ((comp) & SK_DBG_CHKMOD(pAC)) && 	\
-		      ((cat) & SK_DBG_CHKCAT(pAC)) ) { 	\
+		if ( ((comp) & SK_DBG_CHKMOD(pAC)) &&	\
+		      ((cat) & SK_DBG_CHKCAT(pAC)) ) {	\
 			SK_DBG_PRINTF arg ;		\
 		}
 #endif
diff --git a/drivers/net/sk98lin/h/skdrv2nd.h b/drivers/net/sk98lin/h/skdrv2nd.h
index a311827..a55005f 100644
--- a/drivers/net/sk98lin/h/skdrv2nd.h
+++ b/drivers/net/sk98lin/h/skdrv2nd.h
@@ -283,7 +283,7 @@ struct s_TxD {
 
 
 /* definition of flags in descriptor control field */
-#define	RX_CTRL_OWN_BMU 	UINT32_C(0x80000000)
+#define	RX_CTRL_OWN_BMU		UINT32_C(0x80000000)
 #define	RX_CTRL_STF		UINT32_C(0x40000000)
 #define	RX_CTRL_EOF		UINT32_C(0x20000000)
 #define	RX_CTRL_EOB_IRQ		UINT32_C(0x10000000)
@@ -295,7 +295,7 @@ struct s_TxD {
 #define RX_CTRL_CHECK_CSUM	UINT32_C(0x00560000)
 #define	RX_CTRL_LEN_MASK	UINT32_C(0x0000FFFF)
 
-#define	TX_CTRL_OWN_BMU 	UINT32_C(0x80000000)
+#define	TX_CTRL_OWN_BMU		UINT32_C(0x80000000)
 #define	TX_CTRL_STF		UINT32_C(0x40000000)
 #define	TX_CTRL_EOF		UINT32_C(0x20000000)
 #define	TX_CTRL_EOB_IRQ		UINT32_C(0x10000000)
diff --git a/drivers/net/sk98lin/h/skgedrv.h b/drivers/net/sk98lin/h/skgedrv.h
index 72ba9ce..9810b39 100644
--- a/drivers/net/sk98lin/h/skgedrv.h
+++ b/drivers/net/sk98lin/h/skgedrv.h
@@ -58,15 +58,15 @@
  * Usually the events are defined by the destination module.
  * In case of the driver we put the definition of the events here.
  */
-#define SK_DRV_PORT_RESET		 1	/* The port needs to be reset */
-#define SK_DRV_NET_UP   		 2	/* The net is operational */
-#define SK_DRV_NET_DOWN			 3	/* The net is down */
-#define SK_DRV_SWITCH_SOFT		 4	/* Ports switch with both links connected */
-#define SK_DRV_SWITCH_HARD		 5	/* Port switch due to link failure */
-#define SK_DRV_RLMT_SEND		 6	/* Send a RLMT packet */
-#define SK_DRV_ADAP_FAIL		 7	/* The whole adapter fails */
-#define SK_DRV_PORT_FAIL		 8	/* One port fails */
+#define SK_DRV_PORT_RESET	 1	/* The port needs to be reset */
+#define SK_DRV_NET_UP		 2	/* The net is operational */
+#define SK_DRV_NET_DOWN		 3	/* The net is down */
+#define SK_DRV_SWITCH_SOFT	 4	/* Ports switch with both links connected */
+#define SK_DRV_SWITCH_HARD	 5	/* Port switch due to link failure */
+#define SK_DRV_RLMT_SEND	 6	/* Send a RLMT packet */
+#define SK_DRV_ADAP_FAIL	 7	/* The whole adapter fails */
+#define SK_DRV_PORT_FAIL	 8	/* One port fails */
 #define SK_DRV_SWITCH_INTERN	 9	/* Port switch by the driver itself */
-#define SK_DRV_POWER_DOWN		10	/* Power down mode */
+#define SK_DRV_POWER_DOWN	10	/* Power down mode */
 
 #endif	/* __INC_SKGEDRV_H_ */
diff --git a/drivers/net/sk98lin/h/skgehw.h b/drivers/net/sk98lin/h/skgehw.h
index 2c98427..52dc83f 100644
--- a/drivers/net/sk98lin/h/skgehw.h
+++ b/drivers/net/sk98lin/h/skgehw.h
@@ -110,10 +110,10 @@
  *
  * Revision 1.29  1999/01/26 08:55:48  malthoff
  * Bugfix: The 16 bit field relations inside the descriptor are
- * 	endianess dependend if the descriptor reversal feature
- * 	(PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled.
- * 	Drivers which use this feature has to set the define
- * 	SK_USE_REV_DESC.
+ *	endianess dependend if the descriptor reversal feature
+ *	(PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled.
+ *	Drivers which use this feature has to set the define
+ *	SK_USE_REV_DESC.
  *
  * Revision 1.28  1998/12/10 11:10:22  malthoff
  * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted.
@@ -274,7 +274,7 @@ extern "C" {
 #define BIT_10S		(1 << 10)
 #define BIT_9S		(1 << 9)
 #define BIT_8S		(1 << 8)
-#define BIT_7S 		(1 << 7)
+#define BIT_7S		(1 << 7)
 #define BIT_6S		(1 << 6)
 #define BIT_5S		(1 << 5)
 #define BIT_4S		(1 << 4)
@@ -340,27 +340,27 @@ extern "C" {
 #define PCI_SUB_VID		0x2c	/* 16 bit	Subsystem Vendor ID */
 #define PCI_SUB_ID		0x2e	/* 16 bit	Subsystem ID */
 #define PCI_BASE_ROM	0x30	/* 32 bit	Expansion ROM Base Address */
-#define PCI_CAP_PTR		0x34	/*  8 bit 	Capabilities Ptr */
+#define PCI_CAP_PTR		0x34	/*  8 bit	Capabilities Ptr */
 	/* Byte 35..3b:	reserved */
 #define PCI_IRQ_LINE	0x3c	/*  8 bit	Interrupt Line */
 #define PCI_IRQ_PIN		0x3d	/*  8 bit	Interrupt Pin */
 #define PCI_MIN_GNT		0x3e	/*  8 bit	Min_Gnt */
 #define PCI_MAX_LAT		0x3f	/*  8 bit	Max_Lat */
 	/* Device Dependent Region */
-#define PCI_OUR_REG_1	0x40	/* 32 bit 	Our Register 1 */
-#define PCI_OUR_REG_2	0x44	/* 32 bit 	Our Register 2 */
+#define PCI_OUR_REG_1	0x40	/* 32 bit	Our Register 1 */
+#define PCI_OUR_REG_2	0x44	/* 32 bit	Our Register 2 */
 	/* Power Management Region */
-#define PCI_PM_CAP_ID	0x48	/*  8 bit 	Power Management Cap. ID */
-#define PCI_PM_NITEM	0x49	/*  8 bit 	Next Item Ptr */
-#define PCI_PM_CAP_REG	0x4a	/* 16 bit 	Power Management Capabilities */
-#define PCI_PM_CTL_STS	0x4c	/* 16 bit 	Power Manag. Control/Status */
+#define PCI_PM_CAP_ID	0x48	/*  8 bit	Power Management Cap. ID */
+#define PCI_PM_NITEM	0x49	/*  8 bit	Next Item Ptr */
+#define PCI_PM_CAP_REG	0x4a	/* 16 bit	Power Management Capabilities */
+#define PCI_PM_CTL_STS	0x4c	/* 16 bit	Power Manag. Control/Status */
 	/* Byte 0x4e:	reserved */
-#define PCI_PM_DAT_REG	0x4f	/*  8 bit 	Power Manag. Data Register */
+#define PCI_PM_DAT_REG	0x4f	/*  8 bit	Power Manag. Data Register */
 	/* VPD Region */
-#define PCI_VPD_CAP_ID	0x50	/*  8 bit 	VPD Cap. ID */
-#define PCI_VPD_NITEM	0x51	/*  8 bit 	Next Item Ptr */
-#define PCI_VPD_ADR_REG	0x52	/* 16 bit 	VPD Address Register */
-#define PCI_VPD_DAT_REG	0x54	/* 32 bit 	VPD Data Register */
+#define PCI_VPD_CAP_ID	0x50	/*  8 bit	VPD Cap. ID */
+#define PCI_VPD_NITEM	0x51	/*  8 bit	Next Item Ptr */
+#define PCI_VPD_ADR_REG	0x52	/* 16 bit	VPD Address Register */
+#define PCI_VPD_DAT_REG	0x54	/* 32 bit	VPD Data Register */
 	/* Byte 0x58..0xff:	reserved */
 
 /*
@@ -530,7 +530,7 @@ extern "C" {
 #define PCI_PM_STATE_D0		0		/* D0:	Operational (default) */
 #define PCI_PM_STATE_D1		1		/* D1:	(YUKON only) */
 #define PCI_PM_STATE_D2		2		/* D2:	(YUKON only) */
-#define PCI_PM_STATE_D3 	3		/* D3:	HOT, Power Down and Reset */
+#define PCI_PM_STATE_D3		3		/* D3:	HOT, Power Down and Reset */
 
 /* VPD Region */
 /*	PCI_VPD_ADR_REG		16 bit	VPD Address Register */
@@ -602,7 +602,7 @@ extern "C" {
 #define B2_CONN_TYP		0x0118	/*  8 bit	Connector type */
 #define B2_PMD_TYP		0x0119	/*  8 bit	PMD type */
 #define B2_MAC_CFG		0x011a	/*  8 bit	MAC Configuration / Chip Revision */
-#define B2_CHIP_ID		0x011b	/*  8 bit 	Chip Identification Number */
+#define B2_CHIP_ID		0x011b	/*  8 bit	Chip Identification Number */
 	/* Eprom registers are currently of no use */
 #define B2_E_0			0x011c	/*  8 bit	EPROM Byte 0 (ext. SRAM size */
 #define B2_E_1			0x011d	/*  8 bit	EPROM Byte 1 (PHY type) */
@@ -623,7 +623,7 @@ extern "C" {
 #define B2_IRQM_VAL		0x0144	/* 32 bit	IRQ Moderation Timer Value */
 #define B2_IRQM_CTRL	0x0148	/*  8 bit	IRQ Moderation Timer Control */
 #define B2_IRQM_TEST	0x0149	/*  8 bit	IRQ Moderation Timer Test */
-#define B2_IRQM_MSK 	0x014c	/* 32 bit	IRQ Moderation Mask */
+#define B2_IRQM_MSK	0x014c	/* 32 bit	IRQ Moderation Mask */
 #define B2_IRQM_HWE_MSK 0x0150	/* 32 bit	IRQ Moderation HW Error Mask */
 	/* 0x0154 - 0x0157:	reserved */
 #define B2_TST_CTRL1	0x0158	/*  8 bit	Test Control Register 1 */
@@ -805,7 +805,7 @@ extern "C" {
  * use MR_ADDR() to access
  */
 #define RX_MFF_EA		0x0c00	/* 32 bit	Receive MAC FIFO End Address */
-#define RX_MFF_WP		0x0c04	/* 32 bit 	Receive MAC FIFO Write Pointer */
+#define RX_MFF_WP		0x0c04	/* 32 bit	Receive MAC FIFO Write Pointer */
 	/* 0x0c08 - 0x0c0b:	reserved */
 #define RX_MFF_RP		0x0c0c	/* 32 bit	Receive MAC FIFO Read Pointer */
 #define RX_MFF_PC		0x0c10	/* 32 bit	Receive MAC FIFO Packet Cnt */
@@ -837,13 +837,13 @@ extern "C" {
 #define RX_GMF_FL_MSK	0x0c4c	/* 32 bit	Rx GMAC FIFO Flush Mask */
 #define RX_GMF_FL_THR	0x0c50	/* 32 bit	Rx GMAC FIFO Flush Threshold */
 	/* 0x0c54 - 0x0c5f:	reserved */
-#define RX_GMF_WP		0x0c60	/* 32 bit 	Rx GMAC FIFO Write Pointer */
+#define RX_GMF_WP		0x0c60	/* 32 bit	Rx GMAC FIFO Write Pointer */
 	/* 0x0c64 - 0x0c67:	reserved */
-#define RX_GMF_WLEV		0x0c68	/* 32 bit 	Rx GMAC FIFO Write Level */
+#define RX_GMF_WLEV		0x0c68	/* 32 bit	Rx GMAC FIFO Write Level */
 	/* 0x0c6c - 0x0c6f:	reserved */
-#define RX_GMF_RP		0x0c70	/* 32 bit 	Rx GMAC FIFO Read Pointer */
+#define RX_GMF_RP		0x0c70	/* 32 bit	Rx GMAC FIFO Read Pointer */
 	/* 0x0c74 - 0x0c77:	reserved */
-#define RX_GMF_RLEV		0x0c78	/* 32 bit 	Rx GMAC FIFO Read Level */
+#define RX_GMF_RLEV		0x0c78	/* 32 bit	Rx GMAC FIFO Read Level */
 	/* 0x0c7c - 0x0c7f:	reserved */
 
 /*
@@ -860,7 +860,7 @@ extern "C" {
  * use MR_ADDR() to access
  */
 #define TX_MFF_EA		0x0d00	/* 32 bit	Transmit MAC FIFO End Address */
-#define TX_MFF_WP		0x0d04	/* 32 bit 	Transmit MAC FIFO WR Pointer */
+#define TX_MFF_WP		0x0d04	/* 32 bit	Transmit MAC FIFO WR Pointer */
 #define TX_MFF_WSP		0x0d08	/* 32 bit	Transmit MAC FIFO WR Shadow Ptr */
 #define TX_MFF_RP		0x0d0c	/* 32 bit	Transmit MAC FIFO RD Pointer */
 #define TX_MFF_PC		0x0d10	/* 32 bit	Transmit MAC FIFO Packet Cnt */
@@ -883,13 +883,13 @@ extern "C" {
 #define TX_GMF_AE_THR	0x0d44	/* 32 bit	Tx GMAC FIFO Almost Empty Thresh.*/
 #define TX_GMF_CTRL_T	0x0d48	/* 32 bit	Tx GMAC FIFO Control/Test */
 	/* 0x0d4c - 0x0d5f:	reserved */
-#define TX_GMF_WP		0x0d60	/* 32 bit 	Tx GMAC FIFO Write Pointer */
-#define TX_GMF_WSP		0x0d64	/* 32 bit 	Tx GMAC FIFO Write Shadow Ptr. */
-#define TX_GMF_WLEV		0x0d68	/* 32 bit 	Tx GMAC FIFO Write Level */
+#define TX_GMF_WP		0x0d60	/* 32 bit	Tx GMAC FIFO Write Pointer */
+#define TX_GMF_WSP		0x0d64	/* 32 bit	Tx GMAC FIFO Write Shadow Ptr. */
+#define TX_GMF_WLEV		0x0d68	/* 32 bit	Tx GMAC FIFO Write Level */
 	/* 0x0d6c - 0x0d6f:	reserved */
-#define TX_GMF_RP		0x0d70	/* 32 bit 	Tx GMAC FIFO Read Pointer */
-#define TX_GMF_RSTP		0x0d74	/* 32 bit 	Tx GMAC FIFO Restart Pointer */
-#define TX_GMF_RLEV		0x0d78	/* 32 bit 	Tx GMAC FIFO Read Level */
+#define TX_GMF_RP		0x0d70	/* 32 bit	Tx GMAC FIFO Read Pointer */
+#define TX_GMF_RSTP		0x0d74	/* 32 bit	Tx GMAC FIFO Restart Pointer */
+#define TX_GMF_RLEV		0x0d78	/* 32 bit	Tx GMAC FIFO Read Level */
 	/* 0x0d7c - 0x0d7f:	reserved */
 
 /*
@@ -1039,8 +1039,8 @@ extern "C" {
 /*	B0_ISRC		32 bit	Interrupt Source Register */
 /*	B0_IMSK		32 bit	Interrupt Mask Register */
 /*	B0_SP_ISRC	32 bit	Special Interrupt Source Reg */
-/*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */
-#define IS_ALL_MSK		0xbfffffffL	/* 		All Interrupt bits */
+/*	B2_IRQM_MSK	32 bit	IRQ Moderation Mask */
+#define IS_ALL_MSK		0xbfffffffL	/*		All Interrupt bits */
 #define IS_HW_ERR		BIT_31		/* Interrupt HW Error */
 								/* Bit 30:	reserved */
 #define IS_PA_TO_RX1	BIT_29		/* Packet Arb Timeout Rx1 */
@@ -1085,7 +1085,7 @@ extern "C" {
 /*	B0_HWE_ISRC	32 bit	HW Error Interrupt Src Reg */
 /*	B0_HWE_IMSK	32 bit	HW Error Interrupt Mask Reg */
 /*	B2_IRQM_HWE_MSK 32 bit	IRQ Moderation HW Error Mask */
-#define IS_ERR_MSK		0x00000fffL	/* 		All Error bits */
+#define IS_ERR_MSK		0x00000fffL	/*		All Error bits */
 								/* Bit 31..14:	reserved */
 #define IS_IRQ_TIST_OV	BIT_13	/* Time Stamp Timer Overflow (YUKON only) */
 #define IS_IRQ_SENSOR	BIT_12	/* IRQ from Sensor (YUKON only) */
@@ -1112,7 +1112,7 @@ extern "C" {
 #define CFG_DIS_M2_CLK	BIT_1S		/* Disable Clock for 2nd MAC */
 #define CFG_SNG_MAC		BIT_0S		/* MAC Config: 0=2 MACs / 1=1 MAC*/
 
-/*	B2_CHIP_ID	 8 bit 	Chip Identification Number */
+/*	B2_CHIP_ID	 8 bit	Chip Identification Number */
 #define CHIP_ID_GENESIS	0x0a		/* Chip ID for GENESIS */
 #define CHIP_ID_YUKON	0xb0		/* Chip ID for YUKON */
 
@@ -1157,7 +1157,7 @@ extern "C" {
 #define DPT_START		BIT_1S	/* Start Descriptor Poll Timer */
 #define DPT_STOP		BIT_0S	/* Stop  Descriptor Poll Timer */
 
-/*	B2_E_3			 8 bit 	lower 4 bits used for HW self test result */
+/*	B2_E_3			 8 bit	lower 4 bits used for HW self test result */
 #define B2_E3_RES_MASK	0x0f
 
 /*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */
@@ -1210,7 +1210,7 @@ extern "C" {
 #define I2C_BURST_LEN	BIT_4		/* Burst Len, 1/4 bytes */
 #define I2C_DEV_SIZE	(7L<<1)		/* Bit	3.. 1:	I2C Device Size	*/
 #define I2C_025K_DEV	(0L<<1)		/*		0: 256 Bytes or smal. */
-#define I2C_05K_DEV		(1L<<1)		/* 		1: 512	Bytes	*/
+#define I2C_05K_DEV		(1L<<1)		/*		1: 512	Bytes	*/
 #define I2C_1K_DEV		(2L<<1)		/*		2: 1024 Bytes	*/
 #define I2C_2K_DEV		(3L<<1)		/*		3: 2048	Bytes	*/
 #define I2C_4K_DEV		(4L<<1)		/*		4: 4096 Bytes	*/
@@ -1417,7 +1417,7 @@ extern "C" {
 #define F_WM_REACHED	BIT_25		/* Watermark reached */
 									/* reserved */
 #define F_FIFO_LEVEL	(0x1fL<<16)	/* Bit 23..16:	# of Qwords in FIFO */
-									/* Bit 15..11: 	reserved */
+									/* Bit 15..11:	reserved */
 #define F_WATER_MARK	0x0007ffL	/* Bit 10.. 0:	Watermark */
 
 /*	Q_T1	32 bit	Test Register 1 */
@@ -1501,12 +1501,12 @@ extern "C" {
 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
 
 /*	RX_MFF_EA	32 bit	Receive MAC FIFO End Address */
-/*	RX_MFF_WP	32 bit 	Receive MAC FIFO Write Pointer */
+/*	RX_MFF_WP	32 bit	Receive MAC FIFO Write Pointer */
 /*	RX_MFF_RP	32 bit	Receive MAC FIFO Read Pointer */
 /*	RX_MFF_PC	32 bit	Receive MAC FIFO Packet Counter */
 /*	RX_MFF_LEV	32 bit	Receive MAC FIFO Level */
 /*	TX_MFF_EA	32 bit	Transmit MAC FIFO End Address */
-/*	TX_MFF_WP	32 bit 	Transmit MAC FIFO Write Pointer */
+/*	TX_MFF_WP	32 bit	Transmit MAC FIFO Write Pointer */
 /*	TX_MFF_WSP	32 bit	Transmit MAC FIFO WR Shadow Pointer */
 /*	TX_MFF_RP	32 bit	Transmit MAC FIFO Read Pointer */
 /*	TX_MFF_PC	32 bit	Transmit MAC FIFO Packet Cnt */
@@ -1553,8 +1553,8 @@ extern "C" {
 
 #define MFF_TX_CTRL_DEF	(MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
 
-/*	RX_MFF_TST2	 	 8 bit	Receive MAC FIFO Test Register 2 */
-/*	TX_MFF_TST2	 	 8 bit	Transmit MAC FIFO Test Register 2 */
+/*	RX_MFF_TST2		 8 bit	Receive MAC FIFO Test Register 2 */
+/*	TX_MFF_TST2		 8 bit	Transmit MAC FIFO Test Register 2 */
 								/* Bit 7:	reserved */
 #define MFF_WSP_T_ON	BIT_6S	/* Tx: Write Shadow Ptr TestOn */
 #define MFF_WSP_T_OFF	BIT_5S	/* Tx: Write Shadow Ptr TstOff */
@@ -1564,8 +1564,8 @@ extern "C" {
 #define MFF_PC_T_OFF	BIT_1S	/* Packet Counter Test Off */
 #define MFF_PC_INC		BIT_0S	/* Packet Counter Increment */
 
-/*	RX_MFF_TST1	 	 8 bit	Receive MAC FIFO Test Register 1 */
-/*	TX_MFF_TST1	 	 8 bit	Transmit MAC FIFO Test Register 1 */
+/*	RX_MFF_TST1		 8 bit	Receive MAC FIFO Test Register 1 */
+/*	TX_MFF_TST1		 8 bit	Transmit MAC FIFO Test Register 1 */
 					/* Bit 7:	reserved */
 #define MFF_WP_T_ON		BIT_6S	/* Write Pointer Test On */
 #define MFF_WP_T_OFF	BIT_5S	/* Write Pointer Test Off */
@@ -1593,7 +1593,7 @@ extern "C" {
 #define LED_START		BIT_2S	/* Start Timer */
 #define LED_STOP		BIT_1S	/* Stop Timer */
 #define LED_STATE		BIT_0S	/* Rx/Tx: LED State, 1=LED on */
-#define LED_CLR_IRQ		BIT_0S	/* Lnk: 	Clear Link IRQ */
+#define LED_CLR_IRQ		BIT_0S	/* Lnk:		Clear Link IRQ */
 
 /*	RX_LED_TST		 8 bit	Receive LED Cnt Test Register */
 /*	TX_LED_TST		 8 bit	Transmit LED Cnt Test Register */
@@ -1603,7 +1603,7 @@ extern "C" {
 #define LED_T_OFF		BIT_1S	/* LED Counter Test mode Off */
 #define LED_T_STEP		BIT_0S	/* LED Counter Step */
 
-/*	LNK_LED_REG	 	 8 bit	Link LED Register */
+/*	LNK_LED_REG		 8 bit	Link LED Register */
 								/* Bit 7.. 6:	reserved */
 #define LED_BLK_ON		BIT_5S	/* Link LED Blinking On */
 #define LED_BLK_OFF		BIT_4S	/* Link LED Blinking Off */
@@ -1616,18 +1616,18 @@ extern "C" {
 
 /*	RX_GMF_EA		32 bit	Rx GMAC FIFO End Address */
 /*	RX_GMF_AF_THR	32 bit	Rx GMAC FIFO Almost Full Thresh. */
-/*	RX_GMF_WP		32 bit 	Rx GMAC FIFO Write Pointer */
-/*	RX_GMF_WLEV		32 bit 	Rx GMAC FIFO Write Level */
-/*	RX_GMF_RP		32 bit 	Rx GMAC FIFO Read Pointer */
-/*	RX_GMF_RLEV		32 bit 	Rx GMAC FIFO Read Level */
+/*	RX_GMF_WP		32 bit	Rx GMAC FIFO Write Pointer */
+/*	RX_GMF_WLEV		32 bit	Rx GMAC FIFO Write Level */
+/*	RX_GMF_RP		32 bit	Rx GMAC FIFO Read Pointer */
+/*	RX_GMF_RLEV		32 bit	Rx GMAC FIFO Read Level */
 /*	TX_GMF_EA		32 bit	Tx GMAC FIFO End Address */
 /*	TX_GMF_AE_THR	32 bit	Tx GMAC FIFO Almost Empty Thresh.*/
-/*	TX_GMF_WP		32 bit 	Tx GMAC FIFO Write Pointer */
-/*	TX_GMF_WSP		32 bit 	Tx GMAC FIFO Write Shadow Ptr. */
-/*	TX_GMF_WLEV		32 bit 	Tx GMAC FIFO Write Level */
-/*	TX_GMF_RP		32 bit 	Tx GMAC FIFO Read Pointer */
-/*	TX_GMF_RSTP		32 bit 	Tx GMAC FIFO Restart Pointer */
-/*	TX_GMF_RLEV		32 bit 	Tx GMAC FIFO Read Level */
+/*	TX_GMF_WP		32 bit	Tx GMAC FIFO Write Pointer */
+/*	TX_GMF_WSP		32 bit	Tx GMAC FIFO Write Shadow Ptr. */
+/*	TX_GMF_WLEV		32 bit	Tx GMAC FIFO Write Level */
+/*	TX_GMF_RP		32 bit	Tx GMAC FIFO Read Pointer */
+/*	TX_GMF_RSTP		32 bit	Tx GMAC FIFO Restart Pointer */
+/*	TX_GMF_RLEV		32 bit	Tx GMAC FIFO Read Level */
 
 /*	RX_GMF_CTRL_T	32 bit	Rx GMAC FIFO Control/Test */
 						/* Bits 31..15:	reserved */
@@ -2211,11 +2211,11 @@ typedef	struct s_HwRxd {
  * PHY_WRITE()		write a 16 bit value to the PHY
  *
  * para:
- * 	IoC		I/O context needed for SK I/O macros
- * 	pPort	Pointer to port struct for PhyAddr
- * 	Mac		XMAC to access		values: MAC_1 or MAC_2
- * 	PhyReg	PHY Register to read or write
- * 	(p)Val	Value or pointer to the value which should be read or
+ *	IoC		I/O context needed for SK I/O macros
+ *	pPort	Pointer to port struct for PhyAddr
+ *	Mac		XMAC to access		values: MAC_1 or MAC_2
+ *	PhyReg	PHY Register to read or write
+ *	(p)Val	Value or pointer to the value which should be read or
  *			written.
  *
  * usage:	PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
@@ -2224,26 +2224,26 @@ typedef	struct s_HwRxd {
  */
 #ifndef DEBUG
 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) {						\
-	SK_U16 Mmu;  														\
+	SK_U16 Mmu;														\
 																		\
 	XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);	\
 	XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));							\
 	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
-		do {  															\
+		do {															\
 			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
 		} while ((Mmu & XM_MMU_PHY_RDY) == 0);							\
 		XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));						\
-	}  																	\
+	}																	\
 }
 #else
 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) {						\
-	SK_U16 Mmu;  														\
+	SK_U16 Mmu;														\
 	int __i = 0;														\
 																		\
 	XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);	\
 	XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));							\
 	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
-		do {  															\
+		do {															\
 			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
 			__i++;														\
 			if (__i > 100000) {											\
@@ -2254,7 +2254,7 @@ typedef	struct s_HwRxd {
 			}															\
 		} while ((Mmu & XM_MMU_PHY_RDY) == 0);							\
 		XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));						\
-	}  																	\
+	}																	\
 }
 #endif /* DEBUG */
 
@@ -2262,17 +2262,17 @@ typedef	struct s_HwRxd {
 	SK_U16 Mmu;															\
 																		\
 	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
-		do {  															\
+		do {															\
 			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
 		} while ((Mmu & XM_MMU_PHY_BUSY) != 0);							\
-	}  																	\
+	}																	\
 	XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);	\
 	XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val));							\
 	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
-		do {  															\
+		do {															\
 			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
 		} while ((Mmu & XM_MMU_PHY_BUSY) != 0);							\
-	}  																	\
+	}																	\
 }
 
 /*
diff --git a/drivers/net/sk98lin/h/skgei2c.h b/drivers/net/sk98lin/h/skgei2c.h
index e639f73..78c25f8 100644
--- a/drivers/net/sk98lin/h/skgei2c.h
+++ b/drivers/net/sk98lin/h/skgei2c.h
@@ -186,7 +186,7 @@
  * To watch the statemachine (JS) use the timer in two ways instead of one as hitherto
  */
 #define	SK_TIMER_WATCH_STATEMACHINE	0	/* Watch the statemachine to finish in a specific time */
-#define	SK_TIMER_NEW_GAUGING    	1	/* Start a new gauging when timer expires */
+#define	SK_TIMER_NEW_GAUGING		1	/* Start a new gauging when timer expires */
 
 
 /*
@@ -200,7 +200,7 @@
 #define	SK_SEN_TEMP_LOW_ERR       0	/* Temperature Low  Err  Threshold */
 
 /* VCC which should be 5 V */
-#define	SK_SEN_PCI_5V_HIGH_ERR  	5588	/* Voltage PCI High Err  Threshold */
+#define	SK_SEN_PCI_5V_HIGH_ERR	5588	/* Voltage PCI High Err  Threshold */
 #define	SK_SEN_PCI_5V_HIGH_WARN     5346	/* Voltage PCI High Warn Threshold */
 #define	SK_SEN_PCI_5V_LOW_WARN		4664	/* Voltage PCI Low  Warn Threshold */
 #define	SK_SEN_PCI_5V_LOW_ERR		4422	/* Voltage PCI Low  Err  Threshold */
@@ -270,10 +270,10 @@
 /*
  * ASIC Core 1V5 voltage (YUKON only)
  */
-#define	SK_SEN_CORE_1V5_HIGH_ERR    1650	/* Voltage ASIC Core High Err Threshold */
+#define	SK_SEN_CORE_1V5_HIGH_ERR	1650	/* Voltage ASIC Core High Err Threshold */
 #define	SK_SEN_CORE_1V5_HIGH_WARN	1575	/* Voltage ASIC Core High Warn Threshold */
 #define	SK_SEN_CORE_1V5_LOW_WARN	1425	/* Voltage ASIC Core Low Warn Threshold */
-#define	SK_SEN_CORE_1V5_LOW_ERR 	1350	/* Voltage ASIC Core Low Err Threshold */
+#define	SK_SEN_CORE_1V5_LOW_ERR		1350	/* Voltage ASIC Core Low Err Threshold */
 
 /*
  * FAN 1 speed
@@ -285,7 +285,7 @@
  */
 #define	SK_SEN_FAN_HIGH_ERR		20000	/* FAN Speed High Err Threshold */
 #define	SK_SEN_FAN_HIGH_WARN	20000	/* FAN Speed High Warn Threshold */
-#define	SK_SEN_FAN_LOW_WARN 	5200	/* FAN Speed Low Warn Threshold */
+#define	SK_SEN_FAN_LOW_WARN	5200	/* FAN Speed Low Warn Threshold */
 #define	SK_SEN_FAN_LOW_ERR		4550	/* FAN Speed Low Err Threshold */
 
 /*
diff --git a/drivers/net/sk98lin/h/skgeinit.h b/drivers/net/sk98lin/h/skgeinit.h
index cdddef9..ef101d7 100644
--- a/drivers/net/sk98lin/h/skgeinit.h
+++ b/drivers/net/sk98lin/h/skgeinit.h
@@ -486,7 +486,7 @@ extern "C" {
 /* Link Speed Current State */
 #define SK_LSPEED_STAT_UNKNOWN		1
 #define SK_LSPEED_STAT_10MBPS		2
-#define SK_LSPEED_STAT_100MBPS 		3
+#define SK_LSPEED_STAT_100MBPS		3
 #define SK_LSPEED_STAT_1000MBPS		4
 #define SK_LSPEED_STAT_INDETERMINATED 5
 
diff --git a/drivers/net/sk98lin/h/skgepnm2.h b/drivers/net/sk98lin/h/skgepnm2.h
index 5c44f47..e812f28 100644
--- a/drivers/net/sk98lin/h/skgepnm2.h
+++ b/drivers/net/sk98lin/h/skgepnm2.h
@@ -248,7 +248,7 @@ typedef struct s_OidTabEntry {
 enum SK_MACSTATS {
 	SK_PNMI_HTX				= 0,
 	SK_PNMI_HTX_OCTET,
-	SK_PNMI_HTX_OCTETHIGH 	= SK_PNMI_HTX_OCTET,
+	SK_PNMI_HTX_OCTETHIGH	= SK_PNMI_HTX_OCTET,
 	SK_PNMI_HTX_OCTETLOW,
 	SK_PNMI_HTX_BROADCAST,
 	SK_PNMI_HTX_MULTICAST,
diff --git a/drivers/net/sk98lin/h/skgepnmi.h b/drivers/net/sk98lin/h/skgepnmi.h
index 7532313..c93e99c 100644
--- a/drivers/net/sk98lin/h/skgepnmi.h
+++ b/drivers/net/sk98lin/h/skgepnmi.h
@@ -67,7 +67,7 @@
  *	Changed macro PHYS2INST. Added pAC to Interface
  *
  *	Revision 1.47  2001/02/07 08:28:23  mkunz
- *	- Added Oids: 	OID_SKGE_DIAG_ACTION
+ *	- Added Oids:	OID_SKGE_DIAG_ACTION
  *					OID_SKGE_DIAG_RESULT
  *					OID_SKGE_MULTICAST_LIST
  *					OID_SKGE_CURRENT_PACKET_FILTER
@@ -253,22 +253,22 @@
 /*
  * Event definitions
  */
-#define SK_PNMI_EVT_SIRQ_OVERFLOW		1	/* Counter overflow */
-#define SK_PNMI_EVT_SEN_WAR_LOW			2	/* Lower war thres exceeded */
-#define SK_PNMI_EVT_SEN_WAR_UPP			3	/* Upper war thres exceeded */
-#define SK_PNMI_EVT_SEN_ERR_LOW			4	/* Lower err thres exceeded */
-#define SK_PNMI_EVT_SEN_ERR_UPP			5	/* Upper err thres exceeded */
-#define SK_PNMI_EVT_CHG_EST_TIMER		6	/* Timer event for RLMT Chg */
+#define SK_PNMI_EVT_SIRQ_OVERFLOW	1	/* Counter overflow */
+#define SK_PNMI_EVT_SEN_WAR_LOW		2	/* Lower war thres exceeded */
+#define SK_PNMI_EVT_SEN_WAR_UPP		3	/* Upper war thres exceeded */
+#define SK_PNMI_EVT_SEN_ERR_LOW		4	/* Lower err thres exceeded */
+#define SK_PNMI_EVT_SEN_ERR_UPP		5	/* Upper err thres exceeded */
+#define SK_PNMI_EVT_CHG_EST_TIMER	6	/* Timer event for RLMT Chg */
 #define SK_PNMI_EVT_UTILIZATION_TIMER	7	/* Timer event for Utiliza. */
-#define SK_PNMI_EVT_CLEAR_COUNTER		8	/* Clear statistic counters */
-#define SK_PNMI_EVT_XMAC_RESET			9	/* XMAC will be reset */
+#define SK_PNMI_EVT_CLEAR_COUNTER	8	/* Clear statistic counters */
+#define SK_PNMI_EVT_XMAC_RESET		9	/* XMAC will be reset */
 
-#define SK_PNMI_EVT_RLMT_PORT_UP		10	/* Port came logically up */
-#define SK_PNMI_EVT_RLMT_PORT_DOWN		11	/* Port went logically down */
+#define SK_PNMI_EVT_RLMT_PORT_UP	10	/* Port came logically up */
+#define SK_PNMI_EVT_RLMT_PORT_DOWN	11	/* Port went logically down */
 #define SK_PNMI_EVT_RLMT_SEGMENTATION	13	/* Two SP root bridges found */
 #define SK_PNMI_EVT_RLMT_ACTIVE_DOWN	14	/* Port went logically down */
-#define SK_PNMI_EVT_RLMT_ACTIVE_UP		15	/* Port came logically up */
-#define SK_PNMI_EVT_RLMT_SET_NETS		16	/* 1. Parameter is number of nets
+#define SK_PNMI_EVT_RLMT_ACTIVE_UP	15	/* Port came logically up */
+#define SK_PNMI_EVT_RLMT_SET_NETS	16	/* 1. Parameter is number of nets
 												1 = single net; 2 = dual net */
 #define SK_PNMI_EVT_VCT_RESET		17	/* VCT port reset timer event started with SET. */
 
@@ -276,14 +276,14 @@
 /*
  * Return values
  */
-#define SK_PNMI_ERR_OK				0
-#define SK_PNMI_ERR_GENERAL			1
+#define SK_PNMI_ERR_OK			0
+#define SK_PNMI_ERR_GENERAL		1
 #define SK_PNMI_ERR_TOO_SHORT		2
 #define SK_PNMI_ERR_BAD_VALUE		3
 #define SK_PNMI_ERR_READ_ONLY		4
 #define SK_PNMI_ERR_UNKNOWN_OID		5
 #define SK_PNMI_ERR_UNKNOWN_INST	6
-#define SK_PNMI_ERR_UNKNOWN_NET 	7
+#define SK_PNMI_ERR_UNKNOWN_NET		7
 
 
 /*
@@ -329,11 +329,11 @@
  */
 #ifndef _NDIS_	/* Check, whether NDIS already included OIDs */
 
-#define OID_GEN_XMIT_OK					0x00020101
-#define OID_GEN_RCV_OK					0x00020102
-#define OID_GEN_XMIT_ERROR				0x00020103
-#define OID_GEN_RCV_ERROR				0x00020104
-#define OID_GEN_RCV_NO_BUFFER			0x00020105
+#define OID_GEN_XMIT_OK			0x00020101
+#define OID_GEN_RCV_OK			0x00020102
+#define OID_GEN_XMIT_ERROR		0x00020103
+#define OID_GEN_RCV_ERROR		0x00020104
+#define OID_GEN_RCV_NO_BUFFER		0x00020105
 
 /* #define OID_GEN_DIRECTED_BYTES_XMIT	0x00020201 */
 #define OID_GEN_DIRECTED_FRAMES_XMIT	0x00020202
@@ -342,27 +342,27 @@
 /* #define OID_GEN_BROADCAST_BYTES_XMIT	0x00020205 */
 #define OID_GEN_BROADCAST_FRAMES_XMIT	0x00020206
 /* #define OID_GEN_DIRECTED_BYTES_RCV	0x00020207 */
-#define OID_GEN_DIRECTED_FRAMES_RCV		0x00020208
+#define OID_GEN_DIRECTED_FRAMES_RCV	0x00020208
 /* #define OID_GEN_MULTICAST_BYTES_RCV	0x00020209 */
 #define OID_GEN_MULTICAST_FRAMES_RCV	0x0002020A
 /* #define OID_GEN_BROADCAST_BYTES_RCV	0x0002020B */
 #define OID_GEN_BROADCAST_FRAMES_RCV	0x0002020C
-#define OID_GEN_RCV_CRC_ERROR			0x0002020D
+#define OID_GEN_RCV_CRC_ERROR		0x0002020D
 #define OID_GEN_TRANSMIT_QUEUE_LENGTH	0x0002020E
 
-#define OID_802_3_PERMANENT_ADDRESS		0x01010101
-#define OID_802_3_CURRENT_ADDRESS		0x01010102
-/* #define OID_802_3_MULTICAST_LIST		0x01010103 */
+#define OID_802_3_PERMANENT_ADDRESS	0x01010101
+#define OID_802_3_CURRENT_ADDRESS	0x01010102
+/* #define OID_802_3_MULTICAST_LIST	0x01010103 */
 /* #define OID_802_3_MAXIMUM_LIST_SIZE	0x01010104 */
-/* #define OID_802_3_MAC_OPTIONS		0x01010105 */
+/* #define OID_802_3_MAC_OPTIONS	0x01010105 */
 
 #define OID_802_3_RCV_ERROR_ALIGNMENT	0x01020101
 #define OID_802_3_XMIT_ONE_COLLISION	0x01020102
 #define OID_802_3_XMIT_MORE_COLLISIONS	0x01020103
-#define OID_802_3_XMIT_DEFERRED			0x01020201
+#define OID_802_3_XMIT_DEFERRED		0x01020201
 #define OID_802_3_XMIT_MAX_COLLISIONS	0x01020202
-#define OID_802_3_RCV_OVERRUN			0x01020203
-#define OID_802_3_XMIT_UNDERRUN			0x01020204
+#define OID_802_3_RCV_OVERRUN		0x01020203
+#define OID_802_3_XMIT_UNDERRUN		0x01020204
 #define OID_802_3_XMIT_TIMES_CRS_LOST	0x01020206
 #define OID_802_3_XMIT_LATE_COLLISIONS	0x01020207
 
@@ -370,193 +370,193 @@
  * PnP and PM OIDs
  */
 #ifdef SK_POWER_MGMT
-#define OID_PNP_CAPABILITIES			0xFD010100
-#define OID_PNP_SET_POWER				0xFD010101
-#define OID_PNP_QUERY_POWER				0xFD010102
-#define OID_PNP_ADD_WAKE_UP_PATTERN		0xFD010103
+#define OID_PNP_CAPABILITIES		0xFD010100
+#define OID_PNP_SET_POWER		0xFD010101
+#define OID_PNP_QUERY_POWER		0xFD010102
+#define OID_PNP_ADD_WAKE_UP_PATTERN	0xFD010103
 #define OID_PNP_REMOVE_WAKE_UP_PATTERN	0xFD010104
-#define OID_PNP_ENABLE_WAKE_UP			0xFD010106
+#define OID_PNP_ENABLE_WAKE_UP		0xFD010106
 #endif /* SK_POWER_MGMT */
 
 #endif /* _NDIS_ */
 
-#define OID_SKGE_MDB_VERSION			0xFF010100
-#define OID_SKGE_SUPPORTED_LIST			0xFF010101
-#define OID_SKGE_VPD_FREE_BYTES			0xFF010102
-#define OID_SKGE_VPD_ENTRIES_LIST		0xFF010103
-#define OID_SKGE_VPD_ENTRIES_NUMBER		0xFF010104
-#define OID_SKGE_VPD_KEY				0xFF010105
-#define OID_SKGE_VPD_VALUE				0xFF010106
-#define OID_SKGE_VPD_ACCESS				0xFF010107
-#define OID_SKGE_VPD_ACTION				0xFF010108
-
-#define OID_SKGE_PORT_NUMBER			0xFF010110
-#define OID_SKGE_DEVICE_TYPE			0xFF010111
-#define OID_SKGE_DRIVER_DESCR			0xFF010112
-#define OID_SKGE_DRIVER_VERSION			0xFF010113
-#define OID_SKGE_HW_DESCR				0xFF010114
-#define OID_SKGE_HW_VERSION				0xFF010115
-#define OID_SKGE_CHIPSET				0xFF010116
-#define OID_SKGE_ACTION					0xFF010117
-#define OID_SKGE_RESULT					0xFF010118
-#define OID_SKGE_BUS_TYPE				0xFF010119
-#define OID_SKGE_BUS_SPEED				0xFF01011A
-#define OID_SKGE_BUS_WIDTH				0xFF01011B
+#define OID_SKGE_MDB_VERSION		0xFF010100
+#define OID_SKGE_SUPPORTED_LIST		0xFF010101
+#define OID_SKGE_VPD_FREE_BYTES		0xFF010102
+#define OID_SKGE_VPD_ENTRIES_LIST	0xFF010103
+#define OID_SKGE_VPD_ENTRIES_NUMBER	0xFF010104
+#define OID_SKGE_VPD_KEY		0xFF010105
+#define OID_SKGE_VPD_VALUE		0xFF010106
+#define OID_SKGE_VPD_ACCESS		0xFF010107
+#define OID_SKGE_VPD_ACTION		0xFF010108
+
+#define OID_SKGE_PORT_NUMBER		0xFF010110
+#define OID_SKGE_DEVICE_TYPE		0xFF010111
+#define OID_SKGE_DRIVER_DESCR		0xFF010112
+#define OID_SKGE_DRIVER_VERSION		0xFF010113
+#define OID_SKGE_HW_DESCR		0xFF010114
+#define OID_SKGE_HW_VERSION		0xFF010115
+#define OID_SKGE_CHIPSET		0xFF010116
+#define OID_SKGE_ACTION			0xFF010117
+#define OID_SKGE_RESULT			0xFF010118
+#define OID_SKGE_BUS_TYPE		0xFF010119
+#define OID_SKGE_BUS_SPEED		0xFF01011A
+#define OID_SKGE_BUS_WIDTH		0xFF01011B
 /* 0xFF01011C unused */
-#define OID_SKGE_DIAG_ACTION			0xFF01011D
-#define OID_SKGE_DIAG_RESULT			0xFF01011E
-#define OID_SKGE_MTU					0xFF01011F
-#define OID_SKGE_PHYS_CUR_ADDR			0xFF010120
-#define OID_SKGE_PHYS_FAC_ADDR			0xFF010121
-#define OID_SKGE_PMD					0xFF010122
-#define OID_SKGE_CONNECTOR				0xFF010123
-#define OID_SKGE_LINK_CAP				0xFF010124
-#define OID_SKGE_LINK_MODE				0xFF010125
-#define OID_SKGE_LINK_MODE_STATUS		0xFF010126
-#define OID_SKGE_LINK_STATUS			0xFF010127
-#define OID_SKGE_FLOWCTRL_CAP			0xFF010128
-#define OID_SKGE_FLOWCTRL_MODE			0xFF010129
-#define OID_SKGE_FLOWCTRL_STATUS		0xFF01012A
-#define OID_SKGE_PHY_OPERATION_CAP		0xFF01012B
-#define OID_SKGE_PHY_OPERATION_MODE		0xFF01012C
+#define OID_SKGE_DIAG_ACTION		0xFF01011D
+#define OID_SKGE_DIAG_RESULT		0xFF01011E
+#define OID_SKGE_MTU			0xFF01011F
+#define OID_SKGE_PHYS_CUR_ADDR		0xFF010120
+#define OID_SKGE_PHYS_FAC_ADDR		0xFF010121
+#define OID_SKGE_PMD			0xFF010122
+#define OID_SKGE_CONNECTOR		0xFF010123
+#define OID_SKGE_LINK_CAP		0xFF010124
+#define OID_SKGE_LINK_MODE		0xFF010125
+#define OID_SKGE_LINK_MODE_STATUS	0xFF010126
+#define OID_SKGE_LINK_STATUS		0xFF010127
+#define OID_SKGE_FLOWCTRL_CAP		0xFF010128
+#define OID_SKGE_FLOWCTRL_MODE		0xFF010129
+#define OID_SKGE_FLOWCTRL_STATUS	0xFF01012A
+#define OID_SKGE_PHY_OPERATION_CAP	0xFF01012B
+#define OID_SKGE_PHY_OPERATION_MODE	0xFF01012C
 #define OID_SKGE_PHY_OPERATION_STATUS	0xFF01012D
-#define OID_SKGE_MULTICAST_LIST			0xFF01012E
+#define OID_SKGE_MULTICAST_LIST		0xFF01012E
 #define OID_SKGE_CURRENT_PACKET_FILTER	0xFF01012F
 
-#define OID_SKGE_TRAP					0xFF010130
-#define OID_SKGE_TRAP_NUMBER			0xFF010131
+#define OID_SKGE_TRAP			0xFF010130
+#define OID_SKGE_TRAP_NUMBER		0xFF010131
 
-#define OID_SKGE_RLMT_MODE				0xFF010140
-#define OID_SKGE_RLMT_PORT_NUMBER		0xFF010141
-#define OID_SKGE_RLMT_PORT_ACTIVE		0xFF010142
+#define OID_SKGE_RLMT_MODE		0xFF010140
+#define OID_SKGE_RLMT_PORT_NUMBER	0xFF010141
+#define OID_SKGE_RLMT_PORT_ACTIVE	0xFF010142
 #define OID_SKGE_RLMT_PORT_PREFERRED	0xFF010143
 #define OID_SKGE_INTERMEDIATE_SUPPORT	0xFF010160
 
-#define OID_SKGE_SPEED_CAP				0xFF010170
-#define OID_SKGE_SPEED_MODE				0xFF010171
-#define OID_SKGE_SPEED_STATUS			0xFF010172
+#define OID_SKGE_SPEED_CAP		0xFF010170
+#define OID_SKGE_SPEED_MODE		0xFF010171
+#define OID_SKGE_SPEED_STATUS		0xFF010172
 
-#define OID_SKGE_SENSOR_NUMBER			0xFF020100
-#define OID_SKGE_SENSOR_INDEX			0xFF020101
-#define OID_SKGE_SENSOR_DESCR			0xFF020102
-#define OID_SKGE_SENSOR_TYPE			0xFF020103
-#define OID_SKGE_SENSOR_VALUE			0xFF020104
+#define OID_SKGE_SENSOR_NUMBER		0xFF020100
+#define OID_SKGE_SENSOR_INDEX		0xFF020101
+#define OID_SKGE_SENSOR_DESCR		0xFF020102
+#define OID_SKGE_SENSOR_TYPE		0xFF020103
+#define OID_SKGE_SENSOR_VALUE		0xFF020104
 #define OID_SKGE_SENSOR_WAR_THRES_LOW	0xFF020105
 #define OID_SKGE_SENSOR_WAR_THRES_UPP	0xFF020106
 #define OID_SKGE_SENSOR_ERR_THRES_LOW	0xFF020107
 #define OID_SKGE_SENSOR_ERR_THRES_UPP	0xFF020108
-#define OID_SKGE_SENSOR_STATUS			0xFF020109
-#define OID_SKGE_SENSOR_WAR_CTS			0xFF02010A
-#define OID_SKGE_SENSOR_ERR_CTS			0xFF02010B
-#define OID_SKGE_SENSOR_WAR_TIME		0xFF02010C
-#define OID_SKGE_SENSOR_ERR_TIME		0xFF02010D
-
-#define OID_SKGE_CHKSM_NUMBER			0xFF020110
-#define OID_SKGE_CHKSM_RX_OK_CTS		0xFF020111
+#define OID_SKGE_SENSOR_STATUS		0xFF020109
+#define OID_SKGE_SENSOR_WAR_CTS		0xFF02010A
+#define OID_SKGE_SENSOR_ERR_CTS		0xFF02010B
+#define OID_SKGE_SENSOR_WAR_TIME	0xFF02010C
+#define OID_SKGE_SENSOR_ERR_TIME	0xFF02010D
+
+#define OID_SKGE_CHKSM_NUMBER		0xFF020110
+#define OID_SKGE_CHKSM_RX_OK_CTS	0xFF020111
 #define OID_SKGE_CHKSM_RX_UNABLE_CTS	0xFF020112
-#define OID_SKGE_CHKSM_RX_ERR_CTS		0xFF020113
-#define OID_SKGE_CHKSM_TX_OK_CTS		0xFF020114
+#define OID_SKGE_CHKSM_RX_ERR_CTS	0xFF020113
+#define OID_SKGE_CHKSM_TX_OK_CTS	0xFF020114
 #define OID_SKGE_CHKSM_TX_UNABLE_CTS	0xFF020115
 
-#define OID_SKGE_STAT_TX				0xFF020120
-#define OID_SKGE_STAT_TX_OCTETS			0xFF020121
-#define OID_SKGE_STAT_TX_BROADCAST		0xFF020122
-#define OID_SKGE_STAT_TX_MULTICAST		0xFF020123
-#define OID_SKGE_STAT_TX_UNICAST		0xFF020124
-#define OID_SKGE_STAT_TX_LONGFRAMES		0xFF020125
-#define OID_SKGE_STAT_TX_BURST			0xFF020126
-#define OID_SKGE_STAT_TX_PFLOWC			0xFF020127
-#define OID_SKGE_STAT_TX_FLOWC			0xFF020128
-#define OID_SKGE_STAT_TX_SINGLE_COL		0xFF020129
-#define OID_SKGE_STAT_TX_MULTI_COL		0xFF02012A
-#define OID_SKGE_STAT_TX_EXCESS_COL		0xFF02012B
-#define OID_SKGE_STAT_TX_LATE_COL		0xFF02012C
-#define OID_SKGE_STAT_TX_DEFFERAL		0xFF02012D
-#define OID_SKGE_STAT_TX_EXCESS_DEF		0xFF02012E
-#define OID_SKGE_STAT_TX_UNDERRUN		0xFF02012F
-#define OID_SKGE_STAT_TX_CARRIER		0xFF020130
-/* #define OID_SKGE_STAT_TX_UTIL		0xFF020131 */
-#define OID_SKGE_STAT_TX_64				0xFF020132
-#define OID_SKGE_STAT_TX_127			0xFF020133
-#define OID_SKGE_STAT_TX_255			0xFF020134
-#define OID_SKGE_STAT_TX_511			0xFF020135
-#define OID_SKGE_STAT_TX_1023			0xFF020136
-#define OID_SKGE_STAT_TX_MAX			0xFF020137
-#define OID_SKGE_STAT_TX_SYNC			0xFF020138
+#define OID_SKGE_STAT_TX		0xFF020120
+#define OID_SKGE_STAT_TX_OCTETS		0xFF020121
+#define OID_SKGE_STAT_TX_BROADCAST	0xFF020122
+#define OID_SKGE_STAT_TX_MULTICAST	0xFF020123
+#define OID_SKGE_STAT_TX_UNICAST	0xFF020124
+#define OID_SKGE_STAT_TX_LONGFRAMES	0xFF020125
+#define OID_SKGE_STAT_TX_BURST		0xFF020126
+#define OID_SKGE_STAT_TX_PFLOWC		0xFF020127
+#define OID_SKGE_STAT_TX_FLOWC		0xFF020128
+#define OID_SKGE_STAT_TX_SINGLE_COL	0xFF020129
+#define OID_SKGE_STAT_TX_MULTI_COL	0xFF02012A
+#define OID_SKGE_STAT_TX_EXCESS_COL	0xFF02012B
+#define OID_SKGE_STAT_TX_LATE_COL	0xFF02012C
+#define OID_SKGE_STAT_TX_DEFFERAL	0xFF02012D
+#define OID_SKGE_STAT_TX_EXCESS_DEF	0xFF02012E
+#define OID_SKGE_STAT_TX_UNDERRUN	0xFF02012F
+#define OID_SKGE_STAT_TX_CARRIER	0xFF020130
+/* #define OID_SKGE_STAT_TX_UTIL	0xFF020131 */
+#define OID_SKGE_STAT_TX_64		0xFF020132
+#define OID_SKGE_STAT_TX_127		0xFF020133
+#define OID_SKGE_STAT_TX_255		0xFF020134
+#define OID_SKGE_STAT_TX_511		0xFF020135
+#define OID_SKGE_STAT_TX_1023		0xFF020136
+#define OID_SKGE_STAT_TX_MAX		0xFF020137
+#define OID_SKGE_STAT_TX_SYNC		0xFF020138
 #define OID_SKGE_STAT_TX_SYNC_OCTETS	0xFF020139
-#define OID_SKGE_STAT_RX				0xFF02013A
-#define OID_SKGE_STAT_RX_OCTETS			0xFF02013B
-#define OID_SKGE_STAT_RX_BROADCAST		0xFF02013C
-#define OID_SKGE_STAT_RX_MULTICAST		0xFF02013D
-#define OID_SKGE_STAT_RX_UNICAST		0xFF02013E
-#define OID_SKGE_STAT_RX_PFLOWC			0xFF02013F
-#define OID_SKGE_STAT_RX_FLOWC			0xFF020140
-#define OID_SKGE_STAT_RX_PFLOWC_ERR		0xFF020141
+#define OID_SKGE_STAT_RX		0xFF02013A
+#define OID_SKGE_STAT_RX_OCTETS		0xFF02013B
+#define OID_SKGE_STAT_RX_BROADCAST	0xFF02013C
+#define OID_SKGE_STAT_RX_MULTICAST	0xFF02013D
+#define OID_SKGE_STAT_RX_UNICAST	0xFF02013E
+#define OID_SKGE_STAT_RX_PFLOWC		0xFF02013F
+#define OID_SKGE_STAT_RX_FLOWC		0xFF020140
+#define OID_SKGE_STAT_RX_PFLOWC_ERR	0xFF020141
 #define OID_SKGE_STAT_RX_FLOWC_UNKWN	0xFF020142
-#define OID_SKGE_STAT_RX_BURST			0xFF020143
-#define OID_SKGE_STAT_RX_MISSED			0xFF020144
-#define OID_SKGE_STAT_RX_FRAMING		0xFF020145
-#define OID_SKGE_STAT_RX_OVERFLOW		0xFF020146
-#define OID_SKGE_STAT_RX_JABBER			0xFF020147
-#define OID_SKGE_STAT_RX_CARRIER		0xFF020148
-#define OID_SKGE_STAT_RX_IR_LENGTH		0xFF020149
-#define OID_SKGE_STAT_RX_SYMBOL			0xFF02014A
-#define OID_SKGE_STAT_RX_SHORTS			0xFF02014B
-#define OID_SKGE_STAT_RX_RUNT			0xFF02014C
-#define OID_SKGE_STAT_RX_CEXT			0xFF02014D
-#define OID_SKGE_STAT_RX_TOO_LONG		0xFF02014E
-#define OID_SKGE_STAT_RX_FCS			0xFF02014F
-/* #define OID_SKGE_STAT_RX_UTIL		0xFF020150 */
-#define OID_SKGE_STAT_RX_64				0xFF020151
-#define OID_SKGE_STAT_RX_127			0xFF020152
-#define OID_SKGE_STAT_RX_255			0xFF020153
-#define OID_SKGE_STAT_RX_511			0xFF020154
-#define OID_SKGE_STAT_RX_1023			0xFF020155
-#define OID_SKGE_STAT_RX_MAX			0xFF020156
-#define OID_SKGE_STAT_RX_LONGFRAMES		0xFF020157
-
-#define OID_SKGE_RLMT_CHANGE_CTS		0xFF020160
-#define OID_SKGE_RLMT_CHANGE_TIME		0xFF020161
-#define OID_SKGE_RLMT_CHANGE_ESTIM		0xFF020162
-#define OID_SKGE_RLMT_CHANGE_THRES		0xFF020163
-
-#define OID_SKGE_RLMT_PORT_INDEX		0xFF020164
-#define OID_SKGE_RLMT_STATUS			0xFF020165
-#define OID_SKGE_RLMT_TX_HELLO_CTS		0xFF020166
-#define OID_SKGE_RLMT_RX_HELLO_CTS		0xFF020167
-#define OID_SKGE_RLMT_TX_SP_REQ_CTS		0xFF020168
-#define OID_SKGE_RLMT_RX_SP_CTS			0xFF020169
+#define OID_SKGE_STAT_RX_BURST		0xFF020143
+#define OID_SKGE_STAT_RX_MISSED		0xFF020144
+#define OID_SKGE_STAT_RX_FRAMING	0xFF020145
+#define OID_SKGE_STAT_RX_OVERFLOW	0xFF020146
+#define OID_SKGE_STAT_RX_JABBER		0xFF020147
+#define OID_SKGE_STAT_RX_CARRIER	0xFF020148
+#define OID_SKGE_STAT_RX_IR_LENGTH	0xFF020149
+#define OID_SKGE_STAT_RX_SYMBOL		0xFF02014A
+#define OID_SKGE_STAT_RX_SHORTS		0xFF02014B
+#define OID_SKGE_STAT_RX_RUNT		0xFF02014C
+#define OID_SKGE_STAT_RX_CEXT		0xFF02014D
+#define OID_SKGE_STAT_RX_TOO_LONG	0xFF02014E
+#define OID_SKGE_STAT_RX_FCS		0xFF02014F
+/* #define OID_SKGE_STAT_RX_UTIL	0xFF020150 */
+#define OID_SKGE_STAT_RX_64		0xFF020151
+#define OID_SKGE_STAT_RX_127		0xFF020152
+#define OID_SKGE_STAT_RX_255		0xFF020153
+#define OID_SKGE_STAT_RX_511		0xFF020154
+#define OID_SKGE_STAT_RX_1023		0xFF020155
+#define OID_SKGE_STAT_RX_MAX		0xFF020156
+#define OID_SKGE_STAT_RX_LONGFRAMES	0xFF020157
+
+#define OID_SKGE_RLMT_CHANGE_CTS	0xFF020160
+#define OID_SKGE_RLMT_CHANGE_TIME	0xFF020161
+#define OID_SKGE_RLMT_CHANGE_ESTIM	0xFF020162
+#define OID_SKGE_RLMT_CHANGE_THRES	0xFF020163
+
+#define OID_SKGE_RLMT_PORT_INDEX	0xFF020164
+#define OID_SKGE_RLMT_STATUS		0xFF020165
+#define OID_SKGE_RLMT_TX_HELLO_CTS	0xFF020166
+#define OID_SKGE_RLMT_RX_HELLO_CTS	0xFF020167
+#define OID_SKGE_RLMT_TX_SP_REQ_CTS	0xFF020168
+#define OID_SKGE_RLMT_RX_SP_CTS		0xFF020169
 
 #define OID_SKGE_RLMT_MONITOR_NUMBER	0xFF010150
-#define OID_SKGE_RLMT_MONITOR_INDEX		0xFF010151
-#define OID_SKGE_RLMT_MONITOR_ADDR		0xFF010152
-#define OID_SKGE_RLMT_MONITOR_ERRS		0xFF010153
+#define OID_SKGE_RLMT_MONITOR_INDEX	0xFF010151
+#define OID_SKGE_RLMT_MONITOR_ADDR	0xFF010152
+#define OID_SKGE_RLMT_MONITOR_ERRS	0xFF010153
 #define OID_SKGE_RLMT_MONITOR_TIMESTAMP	0xFF010154
-#define OID_SKGE_RLMT_MONITOR_ADMIN		0xFF010155
-
-#define OID_SKGE_TX_SW_QUEUE_LEN		0xFF020170
-#define OID_SKGE_TX_SW_QUEUE_MAX		0xFF020171
-#define OID_SKGE_TX_RETRY				0xFF020172
-#define OID_SKGE_RX_INTR_CTS			0xFF020173
-#define OID_SKGE_TX_INTR_CTS			0xFF020174
-#define OID_SKGE_RX_NO_BUF_CTS			0xFF020175
-#define OID_SKGE_TX_NO_BUF_CTS			0xFF020176
-#define OID_SKGE_TX_USED_DESCR_NO		0xFF020177
-#define OID_SKGE_RX_DELIVERED_CTS		0xFF020178
+#define OID_SKGE_RLMT_MONITOR_ADMIN	0xFF010155
+
+#define OID_SKGE_TX_SW_QUEUE_LEN	0xFF020170
+#define OID_SKGE_TX_SW_QUEUE_MAX	0xFF020171
+#define OID_SKGE_TX_RETRY		0xFF020172
+#define OID_SKGE_RX_INTR_CTS		0xFF020173
+#define OID_SKGE_TX_INTR_CTS		0xFF020174
+#define OID_SKGE_RX_NO_BUF_CTS		0xFF020175
+#define OID_SKGE_TX_NO_BUF_CTS		0xFF020176
+#define OID_SKGE_TX_USED_DESCR_NO	0xFF020177
+#define OID_SKGE_RX_DELIVERED_CTS	0xFF020178
 #define OID_SKGE_RX_OCTETS_DELIV_CTS	0xFF020179
-#define OID_SKGE_RX_HW_ERROR_CTS		0xFF02017A
-#define OID_SKGE_TX_HW_ERROR_CTS		0xFF02017B
-#define OID_SKGE_IN_ERRORS_CTS			0xFF02017C
-#define OID_SKGE_OUT_ERROR_CTS			0xFF02017D
-#define OID_SKGE_ERR_RECOVERY_CTS		0xFF02017E
-#define OID_SKGE_SYSUPTIME				0xFF02017F
+#define OID_SKGE_RX_HW_ERROR_CTS	0xFF02017A
+#define OID_SKGE_TX_HW_ERROR_CTS	0xFF02017B
+#define OID_SKGE_IN_ERRORS_CTS		0xFF02017C
+#define OID_SKGE_OUT_ERROR_CTS		0xFF02017D
+#define OID_SKGE_ERR_RECOVERY_CTS	0xFF02017E
+#define OID_SKGE_SYSUPTIME		0xFF02017F
 
-#define OID_SKGE_ALL_DATA				0xFF020190
+#define OID_SKGE_ALL_DATA		0xFF020190
 
 /* Defines for VCT. */
-#define OID_SKGE_VCT_GET			0xFF020200
-#define OID_SKGE_VCT_SET			0xFF020201
-#define OID_SKGE_VCT_STATUS			0xFF020202
+#define OID_SKGE_VCT_GET		0xFF020200
+#define OID_SKGE_VCT_SET		0xFF020201
+#define OID_SKGE_VCT_STATUS		0xFF020202
 
 
 /* VCT struct to store a backup copy of VCT data after a port reset. */
@@ -578,20 +578,20 @@ typedef struct s_PnmiVct {
 
 
 /* VCT cable test status. */
-#define SK_PNMI_VCT_NORMAL_CABLE		0
-#define SK_PNMI_VCT_SHORT_CABLE			1
-#define SK_PNMI_VCT_OPEN_CABLE			2
-#define SK_PNMI_VCT_TEST_FAIL			3
-#define SK_PNMI_VCT_IMPEDANCE_MISMATCH		4
-
-#define	OID_SKGE_TRAP_SEN_WAR_LOW		500
-#define OID_SKGE_TRAP_SEN_WAR_UPP		501
-#define	OID_SKGE_TRAP_SEN_ERR_LOW		502
-#define OID_SKGE_TRAP_SEN_ERR_UPP		503
+#define SK_PNMI_VCT_NORMAL_CABLE	0
+#define SK_PNMI_VCT_SHORT_CABLE		1
+#define SK_PNMI_VCT_OPEN_CABLE		2
+#define SK_PNMI_VCT_TEST_FAIL		3
+#define SK_PNMI_VCT_IMPEDANCE_MISMATCH	4
+
+#define	OID_SKGE_TRAP_SEN_WAR_LOW	500
+#define OID_SKGE_TRAP_SEN_WAR_UPP	501
+#define	OID_SKGE_TRAP_SEN_ERR_LOW	502
+#define OID_SKGE_TRAP_SEN_ERR_UPP	503
 #define OID_SKGE_TRAP_RLMT_CHANGE_THRES	520
 #define OID_SKGE_TRAP_RLMT_CHANGE_PORT	521
 #define OID_SKGE_TRAP_RLMT_PORT_DOWN	522
-#define OID_SKGE_TRAP_RLMT_PORT_UP		523
+#define OID_SKGE_TRAP_RLMT_PORT_UP	523
 #define OID_SKGE_TRAP_RLMT_SEGMENTATION	524
 
 
@@ -775,7 +775,7 @@ typedef struct s_PnmiVct {
 /*
  * Structure definition for SkPnmiGetStruct and SkPnmiSetStruct
  */
-#define SK_PNMI_VPD_KEY_SIZE	5
+#define SK_PNMI_VPD_KEY_SIZE		5
 #define SK_PNMI_VPD_BUFSIZE		(VPD_SIZE)
 #define SK_PNMI_VPD_ENTRIES		(VPD_SIZE / 4)
 #define SK_PNMI_VPD_DATALEN		128 /*  Number of data bytes */
@@ -783,12 +783,12 @@ typedef struct s_PnmiVct {
 #define SK_PNMI_MULTICAST_LISTLEN	64
 #define SK_PNMI_SENSOR_ENTRIES		(SK_MAX_SENSORS)
 #define SK_PNMI_CHECKSUM_ENTRIES	3
-#define SK_PNMI_MAC_ENTRIES			(SK_MAX_MACS + 1)
+#define SK_PNMI_MAC_ENTRIES		(SK_MAX_MACS + 1)
 #define SK_PNMI_MONITOR_ENTRIES		20
 #define SK_PNMI_TRAP_ENTRIES		10
-#define SK_PNMI_TRAPLEN				128
-#define SK_PNMI_STRINGLEN1			80
-#define SK_PNMI_STRINGLEN2			25
+#define SK_PNMI_TRAPLEN			128
+#define SK_PNMI_STRINGLEN1		80
+#define SK_PNMI_STRINGLEN2		25
 #define SK_PNMI_TRAP_QUEUE_LEN		512
 
 typedef struct s_PnmiVpd {
@@ -992,12 +992,12 @@ typedef struct s_PnmiStrucData {
 /*
  * Various definitions
  */
-#define SK_PNMI_MAX_PROTOS		3
+#define SK_PNMI_MAX_PROTOS	3
 
-#define SK_PNMI_CNT_NO			66	/* Must have the value of the enum
-									 * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
-									 * for check while init phase 1
-									 */
+#define SK_PNMI_CNT_NO		66	/* Must have the value of the enum
+					 * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
+					 * for check while init phase 1
+					 */
 
 /*
  * Estimate data structure
@@ -1091,7 +1091,6 @@ typedef struct s_PnmiData {
 	SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS];
 } SK_PNMI;
 
-
 /*
  * Function prototypes
  */
diff --git a/drivers/net/sk98lin/h/skvpd.h b/drivers/net/sk98lin/h/skvpd.h
index 1be34c5..3159e27 100644
--- a/drivers/net/sk98lin/h/skvpd.h
+++ b/drivers/net/sk98lin/h/skvpd.h
@@ -126,7 +126,7 @@
  * Define READ and WRITE Constants.
  */
 
-#define VPD_DEV_ID_GENESIS 	0x4300
+#define VPD_DEV_ID_GENESIS	0x4300
 
 #define	VPD_SIZE_YUKON		256
 #define	VPD_SIZE_GENESIS	512
@@ -223,19 +223,19 @@ typedef	struct s_vpd_key {
 		if ((pAC)->DgT.DgUseCfgCycle)			\
 			SkPciWriteCfgDWord(pAC,Addr,Val);	\
 		else						\
-			SK_OUT32(pAC,PCI_C(Addr),Val); 		\
+			SK_OUT32(pAC,PCI_C(Addr),Val);		\
 		}
 #define VPD_IN8(pAC,Ioc,Addr,pVal) {			\
-		if ((pAC)->DgT.DgUseCfgCycle) 			\
+		if ((pAC)->DgT.DgUseCfgCycle)			\
 			SkPciReadCfgByte(pAC,Addr,pVal);	\
 		else						\
-			SK_IN8(pAC,PCI_C(Addr),pVal); 		\
+			SK_IN8(pAC,PCI_C(Addr),pVal);		\
 		}
 #define VPD_IN16(pAC,Ioc,Addr,pVal) {			\
-		if ((pAC)->DgT.DgUseCfgCycle) 			\
+		if ((pAC)->DgT.DgUseCfgCycle)			\
 			SkPciReadCfgWord(pAC,Addr,pVal);	\
 		else						\
-			SK_IN16(pAC,PCI_C(Addr),pVal); 		\
+			SK_IN16(pAC,PCI_C(Addr),pVal);		\
 		}
 #define VPD_IN32(pAC,Ioc,Addr,pVal) {			\
 		if ((pAC)->DgT.DgUseCfgCycle)			\
diff --git a/drivers/net/sk98lin/h/xmac_ii.h b/drivers/net/sk98lin/h/xmac_ii.h
index 2ef903a..09e21d6 100644
--- a/drivers/net/sk98lin/h/xmac_ii.h
+++ b/drivers/net/sk98lin/h/xmac_ii.h
@@ -237,7 +237,7 @@ extern "C" {
 #define XM_RX_CMD		0x0030	/* 16 bit r/w	Receive Command Register */
 #define XM_PHY_ADDR		0x0034	/* 16 bit r/w	PHY Address Register */
 #define XM_PHY_DATA		0x0038	/* 16 bit r/w	PHY Data Register */
-	/* 0x003c: 		reserved */
+	/* 0x003c:		reserved */
 #define XM_GP_PORT		0x0040	/* 32 bit r/w	General Purpose Port Register */
 #define XM_IMSK			0x0044	/* 16 bit r/w	Interrupt Mask Register */
 #define XM_ISRC			0x0048	/* 16 bit r/o	Interrupt Status Register */
@@ -248,14 +248,14 @@ extern "C" {
 #define XM_TX_THR		0x0064	/* 16 bit r/w	Tx Request Threshold */
 #define XM_HT_THR		0x0066	/* 16 bit r/w	Host Request Threshold */
 #define XM_PAUSE_DA		0x0068	/* NA reg r/w	Pause Destination Address */
-	/* 0x006e: 		reserved */
+	/* 0x006e:		reserved */
 #define XM_CTL_PARA		0x0070	/* 32 bit r/w	Control Parameter Register */
 #define XM_MAC_OPCODE	0x0074	/* 16 bit r/w	Opcode for MAC control frames */
 #define XM_MAC_PTIME	0x0076	/* 16 bit r/w	Pause time for MAC ctrl frames*/
 #define XM_TX_STAT		0x0078	/* 32 bit r/o	Tx Status LIFO Register */
 
 	/* 0x0080 - 0x00fc:	16 NA reg r/w	Exact Match Address Registers */
-	/* 				use the XM_EXM() macro to address */
+	/*				use the XM_EXM() macro to address */
 #define XM_EXM_START	0x0080	/* r/w	Start Address of the EXM Regs */
 
 	/*
@@ -413,7 +413,7 @@ extern "C" {
 #define XM_RX_IPG_CAP	(1<<6)	/* Bit  6	repl. type field with IPG */
 #define XM_RX_TP_MD		(1<<5)	/* Bit  5:	Enable transparent Mode */
 #define XM_RX_STRIP_FCS	(1<<4)	/* Bit  4:	Enable FCS Stripping */
-#define XM_RX_SELF_RX	(1<<3)	/* Bit  3: 	Enable Rx of own packets */
+#define XM_RX_SELF_RX	(1<<3)	/* Bit  3:	Enable Rx of own packets */
 #define XM_RX_SAM_LINE	(1<<2)	/* Bit  2: (sc)	Start utilization calculation */
 #define XM_RX_STRIP_PAD	(1<<1)	/* Bit  1:	Strip pad bytes of Rx frames */
 #define XM_RX_DIS_CEXT	(1<<0)	/* Bit  0:	Disable carrier ext. check */
@@ -510,7 +510,7 @@ extern "C" {
 									/* Bit 31..27:	reserved */
 #define XM_MD_ENA_REJ	(1L<<26)	/* Bit 26:	Enable Frame Reject */
 #define XM_MD_SPOE_E	(1L<<25)	/* Bit 25:	Send Pause on Edge */
-									/* 		extern generated */
+									/*		extern generated */
 #define XM_MD_TX_REP	(1L<<24)	/* Bit 24:	Transmit Repeater Mode */
 #define XM_MD_SPOFF_I	(1L<<23)	/* Bit 23:	Send Pause on FIFO full */
 									/*		intern generated */
@@ -548,7 +548,7 @@ extern "C" {
 								/* Bit 16..6:	reserved */
 #define XM_SC_SNP_RXC	(1<<5)	/* Bit  5: (sc)	Snap Rx Counters */
 #define XM_SC_SNP_TXC	(1<<4)	/* Bit  4: (sc)	Snap Tx Counters */
-#define XM_SC_CP_RXC	(1<<3)	/* Bit  3: 	Copy Rx Counters Continuously */
+#define XM_SC_CP_RXC	(1<<3)	/* Bit  3:	Copy Rx Counters Continuously */
 #define XM_SC_CP_TXC	(1<<2)	/* Bit  2:	Copy Tx Counters Continuously */
 #define XM_SC_CLR_RXC	(1<<1)	/* Bit  1: (sc)	Clear Rx Counters */
 #define XM_SC_CLR_TXC	(1<<0)	/* Bit  0: (sc) Clear Tx Counters */
@@ -1316,7 +1316,7 @@ extern "C" {
 #define PHY_M_PC_DIS_JABBER	(1<<0)	/* Bit  0:	Disable Jabber */
 
 #define PHY_M_PC_MDI_XMODE(x)	SHIFT5(x)
-#define PHY_M_PC_MAN_MDI	0    	/* 00 = Manual MDI configuration */
+#define PHY_M_PC_MAN_MDI	0	/* 00 = Manual MDI configuration */
 #define PHY_M_PC_MAN_MDIX	1		/* 01 = Manual MDIX configuration */
 #define PHY_M_PC_ENA_AUTO	3		/* 11 = Enable Automatic Crossover */