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| author | Tom Rini <trini@konsulko.com> | 2016-04-04 14:34:09 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-04-04 14:34:09 -0400 |
| commit | 4ed6ed3c27a069a00c8a557d606a05276cc4653e (patch) | |
| tree | edb142ac2c9c220f4f422672ae115d85ee831d3e /drivers/net/phy/ti.c | |
| parent | 7e10a7c3bc382ff79bb6746944a0a4a0073a0faf (diff) | |
| parent | 07654ba1e37e0de2ee3a5983ad510a8c2dd21035 (diff) | |
| download | u-boot-imx-4ed6ed3c27a069a00c8a557d606a05276cc4653e.zip u-boot-imx-4ed6ed3c27a069a00c8a557d606a05276cc4653e.tar.gz u-boot-imx-4ed6ed3c27a069a00c8a557d606a05276cc4653e.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Diffstat (limited to 'drivers/net/phy/ti.c')
| -rw-r--r-- | drivers/net/phy/ti.c | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index c3912d5..937426b 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -12,6 +12,8 @@ #define MII_DP83867_PHYCTRL 0x10 #define MII_DP83867_MICR 0x12 +#define MII_DP83867_CFG2 0x14 +#define MII_DP83867_BISCR 0x16 #define DP83867_CTRL 0x1f /* Extended Registers */ @@ -43,10 +45,22 @@ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 #define DP83867_MDI_CROSSOVER 5 #define DP83867_MDI_CROSSOVER_AUTO 2 +#define DP83867_MDI_CROSSOVER_MDIX 2 +#define DP83867_PHYCTRL_SGMIIEN 0x0800 +#define DP83867_PHYCTRL_RXFIFO_SHIFT 12 +#define DP83867_PHYCTRL_TXFIFO_SHIFT 14 /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 +/* CFG2 bits */ +#define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040 +#define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080 +#define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100 +#define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800 +#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000 +#define MII_DP83867_CFG2_MASK 0x003F + #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ @@ -141,7 +155,7 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev) static int dp83867_config(struct phy_device *phydev) { - unsigned int val, delay; + unsigned int val, delay, cfg2; int ret; /* Restart the PHY. */ @@ -155,6 +169,29 @@ static int dp83867_config(struct phy_device *phydev) (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); if (ret) return ret; + } else { + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, + (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000)); + + cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2); + cfg2 &= MII_DP83867_CFG2_MASK; + cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN | + MII_DP83867_CFG2_SGMII_AUTONEGEN | + MII_DP83867_CFG2_SPEEDOPT_ENH | + MII_DP83867_CFG2_SPEEDOPT_CNT | + MII_DP83867_CFG2_SPEEDOPT_INTLOW); + phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2); + + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr, 0x0); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, + DP83867_PHYCTRL_SGMIIEN | + (DP83867_MDI_CROSSOVER_MDIX << + DP83867_MDI_CROSSOVER) | + (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) | + (FIFO_DEPTH << DP83867_PHYCTRL_TXFIFO_SHIFT)); + phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0); } if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && |