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authorWolfgang Denk <wd@denx.de>2008-10-19 02:35:50 +0200
committerWolfgang Denk <wd@denx.de>2008-10-21 11:25:39 +0200
commit8ed44d91c8122d00368523b0b746691c895d3b3c (patch)
tree7e2ff620c5b378aa82208c3e7a99e2a56570ddb7 /drivers/net/ns8382x.c
parent08ef89ecd174969b3544f3f0c7cd1de3c57f737b (diff)
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Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'drivers/net/ns8382x.c')
-rw-r--r--drivers/net/ns8382x.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c
index a2d61af..198f73d 100644
--- a/drivers/net/ns8382x.c
+++ b/drivers/net/ns8382x.c
@@ -445,7 +445,7 @@ ns8382x_initialize(bd_t * bis)
Read and write MII registers using software-generated serial MDIO
protocol. See the MII specifications or DP83840A data sheet for details.
- The maximum data clock rate is 2.5 Mhz. To meet minimum timing we
+ The maximum data clock rate is 2.5 MHz. To meet minimum timing we
must flush writes to the PCI bus with a PCI read. */
#define mdio_delay(mdio_addr) INL(dev, mdio_addr)