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authorFelix Radensky <felix@embedded-sol.com>2009-05-31 20:44:15 +0300
committerBen Warren <biggerbadderben@gmail.com>2009-06-08 22:57:21 -0700
commit0c24dec550ddb7d86b8bfdd8645b18479f73e6e2 (patch)
tree96f0477552ff68214b03adb54ff14152220ea239 /drivers/net/mcffec.c
parentd65e34d12514de2bbe3b8f519761d641c081bad0 (diff)
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ppc4xx/net: Fix MDIO clock setup
This patch fixes MDIO clock setup in case when OPB frequency is 100MHz. Current code assumes that the value of sysinfo.freqOPB is 100000000 when OPB frequency is 100MHz. In reality it is 100000001. As a result MDIO clock is set to incorrect value, larger than 2.5MHz, thus violating the standard. This in not a problem on boards equipped with Marvell PHYs (e.g. Canyonlands), since those PHYs support MDIO clocks up to 8.3MHz, but can be a problem for other PHYs (e.g. Realtek ones). Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Diffstat (limited to 'drivers/net/mcffec.c')
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