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| author | Tom Rini <trini@ti.com> | 2014-02-04 10:22:23 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-04 11:51:20 -0500 |
| commit | b66af14dc9d0bb3b962e09b2d000f228e2d5b039 (patch) | |
| tree | 74cc58551075570603e2ad02ad7eb1cec63d7181 /drivers/net/fm/t1040.c | |
| parent | c61d94d86035ab2165aedf208b8f3c768b277a3d (diff) | |
| parent | 1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba (diff) | |
| download | u-boot-imx-b66af14dc9d0bb3b962e09b2d000f228e2d5b039.zip u-boot-imx-b66af14dc9d0bb3b962e09b2d000f228e2d5b039.tar.gz u-boot-imx-b66af14dc9d0bb3b962e09b2d000f228e2d5b039.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'drivers/net/fm/t1040.c')
| -rw-r--r-- | drivers/net/fm/t1040.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 83cf081..bcc871d 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -12,5 +12,61 @@ phy_interface_t fman_port_enet_if(enum fm_port port) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + /* handle RGMII first */ + if ((port == FM1_DTSEC2) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if ((port == FM1_DTSEC4) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if (port == FM1_DTSEC5) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_QSGMII; + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + return PHY_INTERFACE_MODE_NONE; } |