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authorEric Nelson <eric.nelson@boundarydevices.com>2012-03-15 18:33:25 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-03-29 07:57:20 +0200
commit5c1ad3e6f8ae578bbe30e09652f1531e9bc22031 (patch)
tree65969d30d4140d8dd075d6fcf4da036d3c919e10 /drivers/net/fec_mxc.h
parent2c4b3c19a1fe1c4e9ef1ec457cf34821368288d7 (diff)
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net: fec_mxc: allow use with cache enabled
Ensure that transmit and receive buffers are cache-line aligned. Invalidate cache for each packet as received, update receive buffer descriptors one cache line at a time, flush cache before transmitting. Original patch by Marek: http://lists.denx.de/pipermail/u-boot/2012-February/117695.html Signed-off-by: Eric Nelson <eric.nelson at boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/net/fec_mxc.h')
-rw-r--r--drivers/net/fec_mxc.h19
1 files changed, 1 insertions, 18 deletions
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 2eb7803..852b2e0 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -234,22 +234,6 @@ struct ethernet_regs {
#endif
/**
- * @brief Descriptor buffer alignment
- *
- * i.MX27 requires a 16 byte alignment (but for the first element only)
- */
-#define DB_ALIGNMENT 16
-
-/**
- * @brief Data buffer alignment
- *
- * i.MX27 requires a four byte alignment for transmit and 16 bits
- * alignment for receive so take 16
- * Note: Valid for member data_pointer in struct buffer_descriptor
- */
-#define DB_DATA_ALIGNMENT 16
-
-/**
* @brief Receive & Transmit Buffer Descriptor definitions
*
* Note: The first BD must be aligned (see DB_ALIGNMENT)
@@ -282,8 +266,7 @@ struct fec_priv {
struct fec_bd *tbd_base; /* TBD ring */
int tbd_index; /* next transmit BD to write */
bd_t *bd;
- void *rdb_ptr;
- void *base_ptr;
+ uint8_t *tdb_ptr;
int dev_id;
int phy_id;
struct mii_dev *bus;