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| author | Alexey Brodkin <Alexey.Brodkin@synopsys.com> | 2013-09-25 19:27:48 +0400 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2013-11-22 16:50:55 -0600 |
| commit | ed102be70f762afc39bda165ba57ea84dc9be39e (patch) | |
| tree | 1056dc7f0270deb8db3283264267a486b768ed0e /drivers/net/designware.h | |
| parent | 227ad7b2b6fab024fff6f60613b0e90c9e3a6724 (diff) | |
| download | u-boot-imx-ed102be70f762afc39bda165ba57ea84dc9be39e.zip u-boot-imx-ed102be70f762afc39bda165ba57ea84dc9be39e.tar.gz u-boot-imx-ed102be70f762afc39bda165ba57ea84dc9be39e.tar.bz2 | |
net: designware: Fix alignment of buffer descriptors
It's important that buffer descriptors are aligned in accordance to GMAC
data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes)
for every bus width type.
If buffer descriptor is improperly aligned GMAC discards lower bits of
provided address and as a result reads from improper location that
doesn't match expected fields.
Commit ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple
updates/enhancements to designware.c" introduced another structure
member "link_printed" right before buffer descriptors while "padding"
member was left untouched. This together with alignment of structure
itself to 16-byte boundary forces buffer descriptoprs always to be
4-byte aligned that causes driver complete disfunction if GMAC bus width
is 64 or 128-bit.
Proposed change makes sure all buffer descriptors are 16-byte (128-bit)
aligned.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Patch: 277902
Diffstat (limited to 'drivers/net/designware.h')
| -rw-r--r-- | drivers/net/designware.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/net/designware.h b/drivers/net/designware.h index e80002a..5440c92 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -112,7 +112,7 @@ struct dmamacdescr { u32 dmamac_cntl; void *dmamac_addr; struct dmamacdescr *dmamac_next; -}; +} __aligned(16); /* * txrx_status definitions @@ -224,8 +224,7 @@ struct dw_eth_dev { u32 tx_currdescnum; u32 rx_currdescnum; u32 phy_configured; - int link_printed; - u32 padding; + u32 link_printed; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; @@ -237,7 +236,7 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; struct eth_device *dev; -} __attribute__ ((aligned(8))); +}; /* Speed specific definitions */ #define SPEED_10M 1 |