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author | Dave Liu <daveliu@freescale.com> | 2008-10-23 21:18:53 +0800 |
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committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-10-24 17:29:37 -0500 |
commit | ae5f943ba8ede448a4b1a145fd8911856701ecc5 (patch) | |
tree | ebf3d075628bb6dd14b8f6dc1ab0b01fd6515d5a /drivers/net/ax88796.c | |
parent | d5b693090ed08d24c18491df9d8fc7387b2906f3 (diff) | |
download | u-boot-imx-ae5f943ba8ede448a4b1a145fd8911856701ecc5.zip u-boot-imx-ae5f943ba8ede448a4b1a145fd8911856701ecc5.tar.gz u-boot-imx-ae5f943ba8ede448a4b1a145fd8911856701ecc5.tar.bz2 |
85xx: Fix the incorrect register used for DDR erratum1
The 8572 DDR erratum1:
DDR controller may enter an illegal state when operating
in 32-bit bus mode with 4-beat bursts.
Description:
When operating with a 32-bit bus, it is recommended that
DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
This forces the DDR controller to use 4-beat bursts when
communicating to the DRAMs. However, an issue exists that
could lead to data corruption when the DDR controller is
in 32-bit bus mode while using 4-beat bursts.
Projected Impact:
If the DDR controller is operating in 32-bit bus mode with
4-beat bursts, then the controller may enter into a bad state.
All subsequent reads from memory is corrupted.
Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
Therefore, this erratum does not affect DDR3 mode.
Work Arounds:
To work around this issue, software must set DEBUG_1[31] in
DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
and CCSRBAR offset + 0x6f00 for DDR_2).
Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
as condition, but it should be DDR_SDRAM_CFG register.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'drivers/net/ax88796.c')
0 files changed, 0 insertions, 0 deletions