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| author | Hoan Hoang <hnhoan@i-syst.com> | 2010-05-11 02:42:38 -0400 |
|---|---|---|
| committer | Ben Warren <biggerbadderben@gmail.com> | 2010-07-12 00:14:29 -0700 |
| commit | 256670680b058105bb948c9f55e11db7ed949fa9 (patch) | |
| tree | aec168eacbb0b933de2c7f017a340c61d23b374f /drivers/net/ax88180.h | |
| parent | 6bb46790178d111161a487cbd847dd2dba37ca24 (diff) | |
| download | u-boot-imx-256670680b058105bb948c9f55e11db7ed949fa9.zip u-boot-imx-256670680b058105bb948c9f55e11db7ed949fa9.tar.gz u-boot-imx-256670680b058105bb948c9f55e11db7ed949fa9.tar.bz2 | |
AX88180: add support for the Marvell 88E1118 phy
Some places in the current code equate the Marvell 88E1111 PHY as the family
when in reality it's a subpart of the Alaska family. So once we generalize
that, add support for the 88E1118 PHY.
Signed-off-by: Hoan Hoang <hnhoan@i-syst.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Diffstat (limited to 'drivers/net/ax88180.h')
| -rw-r--r-- | drivers/net/ax88180.h | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h index c793e92..f26a91b 100644 --- a/drivers/net/ax88180.h +++ b/drivers/net/ax88180.h @@ -33,6 +33,7 @@ struct ax88180_private { unsigned char PadSize; unsigned short PhyAddr; unsigned short PhyID0; + unsigned short PhyID1; unsigned short FirstTxDesc; unsigned short NextTxDesc; ax88180_link_state LinkState; @@ -63,7 +64,8 @@ struct ax88180_private { /* Max Rx Jumbo size is 15K Bytes */ #define MAX_RX_SIZE 0x3C00 -#define MARVELL_88E1111_PHYSID0 0x0141 +#define MARVELL_ALASKA_PHYSID0 0x141 +#define MARVELL_88E1118_PHYSID1 0xE40 #define CICADA_CIS8201_PHYSID0 0x000F @@ -296,14 +298,36 @@ struct ax88180_private { #define LINK_CHANGE_INT 0x0400 #define M88_ISR 0x0013 #define LINK_CHANGE_STATUS 0x0400 -#define M88_EXT_SCR 0x0014 +#define M88E1111_EXT_SCR 0x0014 #define RGMII_RXCLK_DELAY 0x0080 #define RGMII_TXCLK_DELAY 0x0002 #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY) -#define M88_EXT_SSR 0x001B +#define M88E1111_EXT_SSR 0x001B #define HWCFG_MODE_MASK 0x000F #define RGMII_COPPER_MODE 0x000B +/* Marvell 88E1118 Gigabit PHY Register Definition */ +#define M88E1118_CR 0x14 + #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020 + #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010 + #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \ + M88E1118_CR_RGMII_RXCLK_DELAY) +#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */ + #define M88E1118_LEDCTL_LED2INT 0x200 + #define M88E1118_LEDCTL_LED2BLNK 0x400 + #define M88E1118_LEDCTL_LED0DUALMODE1 0xc + #define M88E1118_LEDCTL_LED0DUALMODE2 0xd + #define M88E1118_LEDCTL_LED0DUALMODE3 0xe + #define M88E1118_LEDCTL_LED0DUALMODE4 0xf + #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \ + M88E1118_LEDCTL_LED0DUALMODE4) + +#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */ + #define M88E1118_LEDMIX_LED050 0x4 + #define M88E1118_LEDMIX_LED150 0x8 + +#define M88E1118_PAGE_SEL 0x16 /* Reg page select */ + /* CICADA CIS8201 Gigabit PHY Register Definition */ #define CIS_IMR 0x0019 #define CIS_INT_ENABLE 0x8000 |