Revert "sf: Fix quad bit set for micron devices"

This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe.

Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
Configuration Register (EVCR), Micron memories expect ALL commands to use
the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer
accepted.

Within the reverted commit, the write_evcr() function is implemented using
the spi_flash_write_common(), which is a shortcut for the
[ spi_flash_cmd_write_enable(), spi_flash_cmd_write(),
spi_flash_cmd_wait_ready() ] sequence.

Since the internal state of the Micron memory has been changed when the
spi_flash_cmd_write() function completes, the later call of the
spi_flash_cmd_wait_ready() function fails.

Indeed the SPI controller driver is not aware of the SPI protocol switch.

Further patches will fix the support of Micron QSPI memories.

Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
[Rebase on master, use JEDEC_MFR(info) in place of idcode0]
Signed-off-by: Jagan Teki <jagan@openedev.com>

2 files changed, 2 insertions, 63 deletions

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 2463686..839cdbe 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -49,7 +49,6 @@ enum spi_nor_option_flags {
 #define CMD_WRITE_DISABLE		0x04
 #define CMD_WRITE_ENABLE		0x06
 #define CMD_QUAD_PAGE_PROGRAM		0x32
-#define CMD_WRITE_EVCR			0x61
 
 /* Read commands */
 #define CMD_READ_ARRAY_SLOW		0x03
@@ -63,7 +62,6 @@ enum spi_nor_option_flags {
 #define CMD_READ_STATUS1		0x35
 #define CMD_READ_CONFIG			0x35
 #define CMD_FLAG_STATUS			0x70
-#define CMD_READ_EVCR			0x65
 
 /* Bank addr access commands */
 #ifdef CONFIG_SPI_FLASH_BAR
@@ -78,7 +76,6 @@ enum spi_nor_option_flags {
 #define STATUS_QEB_WINSPAN		BIT(1)
 #define STATUS_QEB_MXIC			BIT(6)
 #define STATUS_PEC			BIT(7)
-#define STATUS_QEB_MICRON		BIT(7)
 #define SR_BP0				BIT(2)  /* Block protect 0 */
 #define SR_BP1				BIT(3)  /* Block protect 1 */
 #define SR_BP2				BIT(4)  /* Block protect 2 */
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index b902540..2e378dc 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -112,37 +112,6 @@ static int write_cr(struct spi_flash *flash, u8 wc)
 }
 #endif
 
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int read_evcr(struct spi_flash *flash, u8 *evcr)
-{
-	int ret;
-	const u8 cmd = CMD_READ_EVCR;
-
-	ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
-	if (ret < 0) {
-		debug("SF: error reading EVCR\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int write_evcr(struct spi_flash *flash, u8 evcr)
-{
-	u8 cmd;
-	int ret;
-
-	cmd = CMD_WRITE_EVCR;
-	ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
-	if (ret < 0) {
-		debug("SF: error while writing EVCR register\n");
-		return ret;
-	}
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_SPI_FLASH_BAR
 static int write_bar(struct spi_flash *flash, u32 offset)
 {
@@ -894,34 +863,6 @@ static int spansion_quad_enable(struct spi_flash *flash)
 }
 #endif
 
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int micron_quad_enable(struct spi_flash *flash)
-{
-	u8 qeb_status;
-	int ret;
-
-	ret = read_evcr(flash, &qeb_status);
-	if (ret < 0)
-		return ret;
-
-	if (!(qeb_status & STATUS_QEB_MICRON))
-		return 0;
-
-	ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
-	if (ret < 0)
-		return ret;
-
-	/* read EVCR and check it */
-	ret = read_evcr(flash, &qeb_status);
-	if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
-		printf("SF: Micron EVCR Quad bit not clear\n");
-		return -EINVAL;
-	}
-
-	return ret;
-}
-#endif
-
 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
 {
 	int				tmp;
@@ -962,7 +903,8 @@ static int set_quad_mode(struct spi_flash *flash,
 #endif
 #ifdef CONFIG_SPI_FLASH_STMICRO
 	case SPI_FLASH_CFI_MFR_STMICRO:
-		return micron_quad_enable(flash);
+		debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
+		return 0;
 #endif
 	default:
 		printf("SF: Need set QEB func for %02x flash\n",