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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2012-11-07 21:52:27 +0000 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2012-12-21 15:34:54 -0600 |
| commit | ba427678a419a59c091e1c816c13852fa05b24bf (patch) | |
| tree | f5da906abcbf33430b5b32e0edece6d21800c197 /drivers/mtd | |
| parent | 42e1321874f8a51373972c293f369c6973c85339 (diff) | |
| download | u-boot-imx-ba427678a419a59c091e1c816c13852fa05b24bf.zip u-boot-imx-ba427678a419a59c091e1c816c13852fa05b24bf.tar.gz u-boot-imx-ba427678a419a59c091e1c816c13852fa05b24bf.tar.bz2 | |
driver/mtd/IFC:Wait tWB time, poll R/B before command execution
IFC_FIR_OP_CMD0 issues command for execution without checking flash
readiness. It may cause problem if flash is not ready. Instead use
IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or
time-out, before issuing command.
NAND_CMD_READID command implemention does not fulfill above requirement. So
update its programming.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Hemant Nautiyal <hemant.nautiyal@freescale.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/nand/fsl_ifc_nand.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 0878bec..b13d8a9 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -391,7 +391,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, timing = IFC_FIR_OP_RBCD; out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (timing << IFC_NAND_FIR0_OP2_SHIFT)); out_be32(&ifc->ifc_nand.nand_fcr0, @@ -758,7 +758,7 @@ static void fsl_ifc_sram_init(void) /* READID */ out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); out_be32(&ifc->ifc_nand.nand_fcr0, |