diff options
author | Wolfgang Denk <wd@denx.de> | 2010-12-22 21:16:17 +0100 |
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committer | Wolfgang Denk <wd@denx.de> | 2010-12-22 21:16:17 +0100 |
commit | cdc51c294ad33879c4e57edf4c9d2155381b1d59 (patch) | |
tree | fc1c3f2c23a2507e91358a6a6dfa881965bf603f /drivers/mtd | |
parent | 250ef029844be2cb98635f265359396866d1749f (diff) | |
parent | b8339e2b9f32663411dba0f48e25b23f542d53bc (diff) | |
download | u-boot-imx-cdc51c294ad33879c4e57edf4c9d2155381b1d59.zip u-boot-imx-cdc51c294ad33879c4e57edf4c9d2155381b1d59.tar.gz u-boot-imx-cdc51c294ad33879c4e57edf4c9d2155381b1d59.tar.bz2 |
Merge branch 'next' of ../next
Diffstat (limited to 'drivers/mtd')
-rw-r--r-- | drivers/mtd/cfi_flash.c | 61 | ||||
-rw-r--r-- | drivers/mtd/nand/nand_base.c | 21 | ||||
-rw-r--r-- | drivers/mtd/nand/nand_ids.c | 4 | ||||
-rw-r--r-- | drivers/mtd/spi/Makefile | 1 | ||||
-rw-r--r-- | drivers/mtd/spi/eon.c | 275 | ||||
-rw-r--r-- | drivers/mtd/spi/spi_flash.c | 3 | ||||
-rw-r--r-- | drivers/mtd/spi/spi_flash_internal.h | 1 | ||||
-rw-r--r-- | drivers/mtd/spi/winbond.c | 39 |
8 files changed, 381 insertions, 24 deletions
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 39c235e..b006884 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -74,6 +74,20 @@ flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #endif +/* + * 0xffff is an undefined value for the configuration register. When + * this value is returned, the configuration register shall not be + * written at all (default mode). + */ +static u16 cfi_flash_config_reg(int i) +{ +#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS + return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i]; +#else + return 0xffff; +#endif +} + #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; #endif @@ -1112,18 +1126,18 @@ static int sector_erased(flash_info_t *info, int i) { int k; int size; - volatile unsigned long *flash; + u32 *flash; /* * Check if whole sector is erased */ size = flash_sector_size(info, i); - flash = (volatile unsigned long *) info->start[i]; + flash = (u32 *)info->start[i]; /* divide by 4 for longword access */ size = size >> 2; for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) + if (flash_read32(flash++) != 0xffffffff) return 0; /* not erased */ } @@ -1426,6 +1440,11 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) #endif }; + /* + * Flash needs to be in status register read mode for + * flash_full_status_check() to work correctly + */ + flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); if ((retcode = flash_full_status_check (info, sector, info->erase_blk_tout, prot ? "protect" : "unprotect")) == 0) { @@ -1975,6 +1994,13 @@ ulong flash_get_size (phys_addr_t base, int banknum) case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: + /* + * Set flash to read-id mode. Otherwise + * reading protected status is not + * guaranteed. + */ + flash_write_cmd(info, sect_cnt, 0, + FLASH_CMD_READ_ID); info->protect[sect_cnt] = flash_isset (info, sect_cnt, FLASH_OFFSET_PROTECT, @@ -2021,6 +2047,31 @@ void flash_set_verbose(uint v) flash_verbose = v; } +static void cfi_flash_set_config_reg(u32 base, u16 val) +{ +#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS + /* + * Only set this config register if really defined + * to a valid value (0xffff is invalid) + */ + if (val == 0xffff) + return; + + /* + * Set configuration register. Data is "encrypted" in the 16 lower + * address bits. + */ + flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1))); + flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1))); + + /* + * Finally issue reset-command to bring device back to + * read-array mode + */ + flash_write16(FLASH_CMD_RESET, (void *)base); +#endif +} + /*----------------------------------------------------------------------- */ unsigned long flash_init (void) @@ -2044,6 +2095,10 @@ unsigned long flash_init (void) for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; + /* Optionally write flash configuration register */ + cfi_flash_set_config_reg(cfi_flash_bank_addr(i), + cfi_flash_config_reg(i)); + if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) flash_get_size(cfi_flash_bank_addr(i), i); size += flash_info[i].size; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 21cc5a3..5239c1f 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -439,11 +439,12 @@ void nand_wait_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; u32 timeo = (CONFIG_SYS_HZ * 20) / 1000; + u32 time_start; - reset_timer(); + time_start = get_timer(0); /* wait until command is processed or timeout occures */ - while (get_timer(0) < timeo) { + while (get_timer(time_start) < timeo) { if (chip->dev_ready) if (chip->dev_ready(mtd)) break; @@ -704,6 +705,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) { unsigned long timeo; int state = this->state; + u32 time_start; if (state == FL_ERASING) timeo = (CONFIG_SYS_HZ * 400) / 1000; @@ -715,10 +717,10 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) else this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); - reset_timer(); + time_start = get_timer(0); while (1) { - if (get_timer(0) > timeo) { + if (get_timer(time_start) > timeo) { printf("Timeout!"); return 0x01; } @@ -732,8 +734,9 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) } } #ifdef PPCHAMELON_NAND_TIMER_HACK - reset_timer(); - while (get_timer(0) < 10); + time_start = get_timer(0); + while (get_timer(time_start) < 10) + ; #endif /* PPCHAMELON_NAND_TIMER_HACK */ return this->read_byte(mtd); @@ -2409,11 +2412,11 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) /* * Get the flash and manufacturer id and lookup if the type is supported */ -static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, +static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, struct nand_chip *chip, int busw, int *maf_id) { - struct nand_flash_dev *type = NULL; + const struct nand_flash_dev *type = NULL; int i, dev_id, maf_idx; int tmp_id, tmp_manf; @@ -2587,7 +2590,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips) { int i, busw, nand_maf_id; struct nand_chip *chip = mtd->priv; - struct nand_flash_dev *type; + const struct nand_flash_dev *type; /* Get buswidth to select the correct functions */ busw = chip->options & NAND_BUSWIDTH_16; diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 25b22ec..8d7ea76 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -22,7 +22,7 @@ + 256 256 Byte page size * 512 512 Byte page size */ -struct nand_flash_dev nand_flash_ids[] = { +const struct nand_flash_dev nand_flash_ids[] = { #ifdef CONFIG_MTD_NAND_MUSEUM_IDS {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, @@ -132,7 +132,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* * Manufacturer ID list */ -struct nand_manufacturers nand_manuf_ids[] = { +const struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_TOSHIBA, "Toshiba"}, {NAND_MFR_SAMSUNG, "Samsung"}, {NAND_MFR_FUJITSU, "Fujitsu"}, diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 3d607c0..57112af 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libspi_flash.o COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o +COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c new file mode 100644 index 0000000..02c3bb9 --- /dev/null +++ b/drivers/mtd/spi/eon.c @@ -0,0 +1,275 @@ +/* + * (C) Copyright 2010, ucRobotics Inc. + * Author: Chong Huang <chuang@ucrobotics.com> + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <malloc.h> +#include <spi_flash.h> + +#include "spi_flash_internal.h" + +/* EN25Q128-specific commands */ +#define CMD_EN25Q128_WREN 0x06 /* Write Enable */ +#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */ +#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */ +#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */ +#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */ +#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_EN25Q128_PP 0x02 /* Page Program */ +#define CMD_EN25Q128_SE 0x20 /* Sector Erase */ +#define CMD_EN25Q128_BE 0xd8 /* Block Erase */ +#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ +#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */ + +#define EON_ID_EN25Q128 0x18 + +#define EON_SR_WIP (1 << 0) /* Write-in-Progress */ + +struct eon_spi_flash_params { + u8 idcode1; + u16 page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_sectors; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct eon_spi_flash { + struct spi_flash flash; + const struct eon_spi_flash_params *params; +}; + +static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct eon_spi_flash, flash); +} + +static const struct eon_spi_flash_params eon_spi_flash_table[] = { + { + .idcode1 = EON_ID_EN25Q128, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 4096, + .name = "EN25Q128", + }, +}; + +static int eon_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + int ret; + u8 cmd = CMD_EN25Q128_RDSR; + u8 status; + + ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); + if (ret) { + debug("SF: Failed to send command %02x: %d\n", cmd, ret); + return ret; + } + + timebase = get_timer(0); + do { + ret = spi_xfer(spi, 8, NULL, &status, 0); + if (ret) + return -1; + + if ((status & EON_SR_WIP) == 0) + break; + + } while (get_timer(timebase) < timeout); + + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); + + if ((status & EON_SR_WIP) == 0) + return 0; + + /* Timed out */ + return -1; +} + +static int eon_read_fast(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + struct eon_spi_flash *eon = to_eon_spi_flash(flash); + unsigned long page_addr; + unsigned long page_size; + u8 cmd[5]; + + page_size = eon->params->page_size; + page_addr = offset / page_size; + + cmd[0] = CMD_READ_ARRAY_FAST; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = offset % page_size; + cmd[4] = 0x00; + + return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); +} + +static int eon_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct eon_spi_flash *eon = to_eon_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = eon->params->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_EN25Q128_PP; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + debug + ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: EON Page Program failed\n"); + break; + } + + ret = eon_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: EON page programming timed out\n"); + break; + } + + page_addr++; + byte_addr = 0; + } + + debug("SF: EON: Successfully programmed %u bytes @ 0x%x\n", + len, offset); + + spi_release_bus(flash->spi); + return ret; +} + +int eon_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + /* block erase */ + struct eon_spi_flash *eon = to_eon_spi_flash(flash); + unsigned long block_size; + size_t actual; + int ret; + u8 cmd[4]; + + + block_size = eon->params->page_size * eon->params->pages_per_sector + * eon->params->sectors_per_block; + + if (offset % block_size || len % block_size) { + debug("SF: Erase offset/length not multiple of block size\n"); + return -1; + } + + len /= block_size; + cmd[0] = CMD_EN25Q128_BE; + cmd[2] = 0x00; + cmd[3] = 0x00; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual++) { + cmd[1] = (offset / block_size) + actual; + ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); + if (ret < 0) { + debug("SF: EON page erase failed\n"); + break; + } + + ret = eon_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT); + if (ret < 0) { + debug("SF: EON page erase timed out\n"); + break; + } + } + + debug("SF: EON: Successfully erased %u bytes @ 0x%x\n", + len * block_size, offset); + + spi_release_bus(flash->spi); + return ret; +} + +struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) +{ + const struct eon_spi_flash_params *params; + struct eon_spi_flash *eon; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) { + params = &eon_spi_flash_table[i]; + if (params->idcode1 == idcode[2]) + break; + } + + if (i == ARRAY_SIZE(eon_spi_flash_table)) { + debug("SF: Unsupported EON ID %02x\n", idcode[1]); + return NULL; + } + + eon = malloc(sizeof(*eon)); + if (!eon) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + + eon->params = params; + eon->flash.spi = spi; + eon->flash.name = params->name; + + eon->flash.write = eon_write; + eon->flash.erase = eon_erase; + eon->flash.read = eon_read_fast; + eon->flash.size = params->page_size * params->pages_per_sector + * params->nr_sectors; + + debug("SF: Detected %s with page size %u, total %u bytes\n", + params->name, params->page_size, eon->flash.size); + + return &eon->flash; +} diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index ab02ef3..b61d219 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -131,6 +131,9 @@ static const struct { #ifdef CONFIG_SPI_FLASH_ATMEL { 0, 0x1f, spi_flash_probe_atmel, }, #endif +#ifdef CONFIG_SPI_FLASH_EON + { 0, 0x1c, spi_flash_probe_eon, }, +#endif #ifdef CONFIG_SPI_FLASH_MACRONIX { 0, 0xc2, spi_flash_probe_macronix, }, #endif diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 9bc43dd..68dcffb 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -46,6 +46,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, /* Manufacturer-specific probe functions */ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c index de3aeb8..4452355 100644 --- a/drivers/mtd/spi/winbond.c +++ b/drivers/mtd/spi/winbond.c @@ -24,11 +24,6 @@ #define CMD_W25_DP 0xb9 /* Deep Power-down */ #define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ -#define WINBOND_ID_W25X16 0x3015 -#define WINBOND_ID_W25X32 0x3016 -#define WINBOND_ID_W25X64 0x3017 -#define WINBOND_ID_W25Q64 0x4017 - #define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */ struct winbond_spi_flash_params { @@ -37,7 +32,7 @@ struct winbond_spi_flash_params { uint8_t l2_page_size; uint16_t pages_per_sector; uint16_t sectors_per_block; - uint8_t nr_blocks; + uint16_t nr_blocks; const char *name; }; @@ -55,7 +50,7 @@ to_winbond_spi_flash(struct spi_flash *flash) static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { { - .id = WINBOND_ID_W25X16, + .id = 0x3015, .l2_page_size = 8, .pages_per_sector = 16, .sectors_per_block = 16, @@ -63,7 +58,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .name = "W25X16", }, { - .id = WINBOND_ID_W25X32, + .id = 0x3016, .l2_page_size = 8, .pages_per_sector = 16, .sectors_per_block = 16, @@ -71,7 +66,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .name = "W25X32", }, { - .id = WINBOND_ID_W25X64, + .id = 0x3017, .l2_page_size = 8, .pages_per_sector = 16, .sectors_per_block = 16, @@ -79,13 +74,37 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .name = "W25X64", }, { - .id = WINBOND_ID_W25Q64, + .id = 0x4015, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "W25Q16", + }, + { + .id = 0x4016, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "W25Q32", + }, + { + .id = 0x4017, .l2_page_size = 8, .pages_per_sector = 16, .sectors_per_block = 16, .nr_blocks = 128, .name = "W25Q64", }, + { + .id = 0x4018, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "W25Q128", + }, }; static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout) |