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| author | Ash Charles <ashcharles@gmail.com> | 2015-02-18 11:25:11 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-05 20:49:43 -0500 |
| commit | b050898efa6b4f0272f12885a7365f044ab4c08e (patch) | |
| tree | 11f53adecf81f4c3732d61ebb43b7288de517856 /drivers/mtd/nand | |
| parent | d8af39337ea82403fb54a9d345d2e47fac4a8460 (diff) | |
| download | u-boot-imx-b050898efa6b4f0272f12885a7365f044ab4c08e.zip u-boot-imx-b050898efa6b4f0272f12885a7365f044ab4c08e.tar.gz u-boot-imx-b050898efa6b4f0272f12885a7365f044ab4c08e.tar.bz2 | |
omap: gpmc: 'nandecc sw' can use HAM1 or BCH8
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw <hamming|bch8>
where 'hamming' is still the default.
Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
Diffstat (limited to 'drivers/mtd/nand')
| -rw-r--r-- | drivers/mtd/nand/omap_gpmc.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index f8b0063..610f969 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -912,8 +912,18 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) return -EINVAL; } } else { - err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, + if (eccstrength == 1) { + err = omap_select_ecc_scheme(nand, + OMAP_ECC_HAM1_CODE_SW, + mtd->writesize, mtd->oobsize); + } else if (eccstrength == 8) { + err = omap_select_ecc_scheme(nand, + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, mtd->writesize, mtd->oobsize); + } else { + printf("nand: error: unsupported ECC scheme\n"); + return -EINVAL; + } } /* Update NAND handling after ECC mode switch */ |