summaryrefslogtreecommitdiff
path: root/drivers/mtd/nand/nand_util.c
diff options
context:
space:
mode:
authorPeter Korsgaard <jacmet@sunsite.dk>2009-12-08 22:20:34 +0100
committerKim Phillips <kim.phillips@freescale.com>2009-12-09 11:40:52 -0600
commit3b887ca8ce72cc12129183538f6e828db13f4867 (patch)
treeec0fa65519ab865973c03620b46ababc987dcd3c /drivers/mtd/nand/nand_util.c
parent386118a896554b13f14ad0f82356276988f7de82 (diff)
downloadu-boot-imx-3b887ca8ce72cc12129183538f6e828db13f4867.zip
u-boot-imx-3b887ca8ce72cc12129183538f6e828db13f4867.tar.gz
u-boot-imx-3b887ca8ce72cc12129183538f6e828db13f4867.tar.bz2
mpc83xx: boot time regression, move LCRR setup back to cpu_init_f
Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields) moved the LCRR assignment to after relocation to RAM because of the potential problem with changing the local bus clock while executing from flash. This change unfortunately adversely affects the boot time, as running all code up to cpu_init_r can cause significant slowdown. E.G. on a 8347 board a bootup time increase of ~600ms has been observed: 0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.168 RS: 232 0.172 I2C: ready 0.176 DRAM: 64 MB 1.236 FLASH: 32 MB Versus: 0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.092 RS: 232 0.092 I2C: ready 0.096 DRAM: 64 MB 0.644 FLASH: 32 MB So far no boards have needed the late LCRR setup, so simply revert it for now - If it is needed at a later time, those boards can either do their own final LCRR setup in board code (E.G. in board_early_init_r), or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do the setup in cpu_init_r. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'drivers/mtd/nand/nand_util.c')
0 files changed, 0 insertions, 0 deletions