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| author | Wolfgang Grandegger <wg@grandegger.com> | 2009-01-16 18:55:54 +0100 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2009-01-23 10:32:51 -0600 |
| commit | 6c869637fef31e66380f0ea1d49690a2e26ec0d7 (patch) | |
| tree | 0ac7c4b616f8a1a725b89ba98585689383f2784e /drivers/mtd/nand/nand_base.c | |
| parent | c70564e6b1bd08f3230182392238907f3531a87e (diff) | |
| download | u-boot-imx-6c869637fef31e66380f0ea1d49690a2e26ec0d7.zip u-boot-imx-6c869637fef31e66380f0ea1d49690a2e26ec0d7.tar.gz u-boot-imx-6c869637fef31e66380f0ea1d49690a2e26ec0d7.tar.bz2 | |
NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
but that's bogus and did not work anyhow.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'drivers/mtd/nand/nand_base.c')
| -rw-r--r-- | drivers/mtd/nand/nand_base.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 94a65d4..ef37f97 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2144,7 +2144,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, { int page, len, status, pages_per_block, ret, chipnr; struct nand_chip *chip = mtd->priv; - int rewrite_bbt[NAND_MAX_CHIPS]={0}; + int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0}; unsigned int bbt_masked_page = 0xffffffff; MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", |