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| author | Wu, Josh <Josh.wu@atmel.com> | 2015-01-16 11:54:46 +0800 |
|---|---|---|
| committer | Andreas Bießmann <andreas.devel@googlemail.com> | 2015-02-07 23:42:57 +0100 |
| commit | 0e48dc5e416f031c8eb05143f2dfab3111ec3b29 (patch) | |
| tree | c0a49ad6b3d6c9938fdde7dc8e1472c26d570f04 /drivers/mtd/nand/atmel_nand_ecc.h | |
| parent | c6941e120386b06b21566b560cd51882b0d1a51a (diff) | |
| download | u-boot-imx-0e48dc5e416f031c8eb05143f2dfab3111ec3b29.zip u-boot-imx-0e48dc5e416f031c8eb05143f2dfab3111ec3b29.tar.gz u-boot-imx-0e48dc5e416f031c8eb05143f2dfab3111ec3b29.tar.bz2 | |
mtd: atmel_nand: according to pmecc version to perform 0xff page correction
As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.
According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'drivers/mtd/nand/atmel_nand_ecc.h')
| -rw-r--r-- | drivers/mtd/nand/atmel_nand_ecc.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h index eac860d..b2d2682 100644 --- a/drivers/mtd/nand/atmel_nand_ecc.h +++ b/drivers/mtd/nand/atmel_nand_ecc.h @@ -123,6 +123,20 @@ struct pmecc_errloc_regs { u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */ u32 el[24]; /* 0x8C-0xE8 Error Location Registers */ u32 reserved1[5]; /* 0xEC-0xFC Reserved */ + + /* + * 0x100-0x1F8: + * Reserved for AT91SAM9X5, AT91SAM9N12. + * HSMC registers for SAMA5D3, SAMA5D4. + */ + u32 reserved2[63]; + + /* + * 0x1FC: + * PMECC version for AT91SAM9X5, AT91SAM9N12. + * HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version. + */ + u32 version; }; /* For Error Location Configuration Register */ @@ -137,6 +151,12 @@ struct pmecc_errloc_regs { #define PMERRLOC_ERR_NUM_MASK (0x1f << 8) #define PMERRLOC_CALC_DONE (1 << 0) +/* PMECC IP version */ +#define PMECC_VERSION_SAMA5D4 0x113 +#define PMECC_VERSION_SAMA5D3 0x112 +#define PMECC_VERSION_AT91SAM9N12 0x102 +#define PMECC_VERSION_AT91SAM9X5 0x101 + /* Galois field dimension */ #define PMECC_GF_DIMENSION_13 13 #define PMECC_GF_DIMENSION_14 14 |